Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective

On metrics of density and power efficiency, neuromorphic technologies have the potential to surpass mainstream computing technologies in tasks where real-time functionality, adaptability, and autonomy are essential. While algorithmic advances in neuromorphic computing are proceeding successfully, the potential of memristors to improve neuromorphic computing have not yet born fruit, primarily because they are often used as a drop-in replacement to conventional memory. However, interdisciplinary approaches anchored in machine learning theory suggest that multifactor plasticity rules matching neural and synaptic dynamics to the device capabilities can take better advantage of memristor dynamics and its stochasticity. Furthermore, such plasticity rules generally show much higher performance than that of classical Spike Time Dependent Plasticity (STDP) rules. This chapter reviews the recent development in learning with spiking neural network models and their possible implementation with memristor-based hardware

An Adaptable Foveating Vision Chip

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A deep learning theory for neural networks grounded in physics

Au cours de la dernière décennie, l'apprentissage profond est devenu une composante majeure de l'intelligence artificielle, ayant mené à une série d'avancées capitales dans une variété de domaines. L'un des piliers de l'apprentissage profond est l'optimisation de fonction de coût par l'algorithme du gradient stochastique (SGD). Traditionnellement en apprentissage profond, les réseaux de neurones sont des fonctions mathématiques différentiables, et les gradients requis pour l'algorithme SGD sont calculés par rétropropagation. Cependant, les architectures informatiques sur lesquelles ces réseaux de neurones sont implémentés et entraînés souffrent d’inefficacités en vitesse et en énergie, dues à la séparation de la mémoire et des calculs dans ces architectures. Pour résoudre ces problèmes, le neuromorphique vise à implementer les réseaux de neurones dans des architectures qui fusionnent mémoire et calculs, imitant plus fidèlement le cerveau. Dans cette thèse, nous soutenons que pour construire efficacement des réseaux de neurones dans des architectures neuromorphiques, il est nécessaire de repenser les algorithmes pour les implémenter et les entraîner. Nous présentons un cadre mathématique alternative, compatible lui aussi avec l’algorithme SGD, qui permet de concevoir des réseaux de neurones dans des substrats qui exploitent mieux les lois de la physique. Notre cadre mathématique s'applique à une très large classe de modèles, à savoir les systèmes dont l'état ou la dynamique sont décrits par des équations variationnelles. La procédure pour calculer les gradients de la fonction de coût dans de tels systèmes (qui dans de nombreux cas pratiques ne nécessite que de l'information locale pour chaque paramètre) est appelée “equilibrium propagation” (EqProp). Comme beaucoup de systèmes en physique et en ingénierie peuvent être décrits par des principes variationnels, notre cadre mathématique peut potentiellement s'appliquer à une grande variété de systèmes physiques, dont les applications vont au delà du neuromorphique et touchent divers champs d'ingénierie.In the last decade, deep learning has become a major component of artificial intelligence, leading to a series of breakthroughs across a wide variety of domains. The workhorse of deep learning is the optimization of loss functions by stochastic gradient descent (SGD). Traditionally in deep learning, neural networks are differentiable mathematical functions, and the loss gradients required for SGD are computed with the backpropagation algorithm. However, the computer architectures on which these neural networks are implemented and trained suffer from speed and energy inefficiency issues, due to the separation of memory and processing in these architectures. To solve these problems, the field of neuromorphic computing aims at implementing neural networks on hardware architectures that merge memory and processing, just like brains do. In this thesis, we argue that building large, fast and efficient neural networks on neuromorphic architectures also requires rethinking the algorithms to implement and train them. We present an alternative mathematical framework, also compatible with SGD, which offers the possibility to design neural networks in substrates that directly exploit the laws of physics. Our framework applies to a very broad class of models, namely those whose state or dynamics are described by variational equations. This includes physical systems whose equilibrium state minimizes an energy function, and physical systems whose trajectory minimizes an action functional (principle of least action). We present a simple procedure to compute the loss gradients in such systems, called equilibrium propagation (EqProp), which requires solely locally available information for each trainable parameter. Since many models in physics and engineering can be described by variational principles, our framework has the potential to be applied to a broad variety of physical systems, whose applications extend to various fields of engineering, beyond neuromorphic computing

A low-power integrated smart sensor with on-chip real-time image processing capabilities

A low-power, CMOS retina with real-time, pixel-level processing capabilities is presented. Features extraction and edge-enhancement are implemented with fully programmable 1D Gabor convolutions. An equivalent computation rate of 3 GOPS is obtained at the cost of very low-power consumption ( W per pixel), providing real-time performances ( microseconds for overall computation, ). Experimental results from the first realized prototype show a very good matching between measures and expected outputs

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work.Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM