Testing Uncovered Interest Parity: A Continuous-Time Approach

Nowadays researchers can choose the sampling frequency of exchange rates and interest rates. If the number of observations per contract period is large relative to the sample size, standard GMM asymptotic theory provides unreliable inferences in UIP regression tests. We specify a bivariate continuous-time model for exchange rates and forward premia robust to temporal aggregation, unlike the discrete time models in the literature. We obtain the UIP restrictions on the continuous-time model parameters, which we estimate efficiently, and propose a novel specification test that compares estimators at different frequencies. Our empirical results based on correctly specified models reject UIP.Exchange rates; Econometric and statistical methods

Testable Design for Positive Control Flipping Faults in Reversible Circuits

Fast computational power is a major concern in every computing system. The advancement of the fabrication process in the present semiconductor technologies provides to accommodate millions of gates per chip and is also capable of reducing the size of the chips. Concurrently, the complex circuit design always leads to high power dissipation and increases the fault rates. Due to these difficulties, researchers explore the reversible logic circuit as an alternative way to implement the low-power circuit design. It is also widely applied in recent technology trends like quantum computing. Analyzing the correct functional behavior of these circuits is an essential requirement in the testing of the circuit. This paper presents a testable design for the k-CNOT based circuit capable of diagnosing the Positive Control Flipping Faults (PCFFs) in reversible circuits. The proposed work shows that generating a single test vector that applies to the constructed design circuit is sufficient for covering the PCFFs in the reversible circuit. Further, the parity-bit operations are augmented to the constructed testable circuit that produces the parity-test pattern to extract the faulty gate location of PCFFs. Various reversible benchmark circuits are used for evaluating the experimental results to establish the correctness of the proposed fault diagnosis technique. Also a comparative analysis is performed with the existing work

DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Investigations into the feasibility of an on-line test methodology

This thesis aims to understand how information coding and the protocol that it supports can affect the characteristics of electronic circuits. More specifically, it investigates an on-line test methodology called IFIS (If it Fails It Stops) and its impact on the design, implementation and subsequent characteristics of circuits intended for application specific lC (ASIC) technology. The first study investigates the influences of information coding and protocol on the characteristics of IFIS systems. The second study investigates methods of circuit design applicable to IFIS cells and identifies the· technique possessing the characteristics most suitable for on-line testing. The third study investigates the characteristics of a 'real-life' commercial UART re-engineered using the techniques resulting from the previous two studies. The final study investigates the effects of the halting properties endowed by the protocol on failure diagnosis within IFIS systems. The outcome of this work is an identification and characterisation of the factors that influence behaviour, implementation costs and the ability to test and diagnose IFIS designs

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43016/1/10836_2004_Article_BF00136077.pd

OLT(RE)2: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems

Reconfigurable systems gained great interest in a wide range of application fields, including aerospace, where electronic devices are exposed to a very harsh working environment. Commercial SRAM-based FPGA devices represent an extremely interesting hardware platform for this kind of systems since they combine low cost with the possibility to utilize state-of-the-art processing power as well as the flexibility of reconfigurable hardware. In this paper we present OLT(RE)2: an on-line on-demand approach to test permanent faults induced by radiation in reconfigurable systems used in space missions. The proposed approach relies on a test circuit and on custom place-and-route algorithms. OLT(RE)2 exploits partial dynamic reconfigurability offered by today’s SRAM-based FPGAs to place the test circuits at run-time. The goal of OLT(RE)2 is to test unprogrammed areas of the FPGA before using them, thus preventing functional modules of the reconfigurable system to be placed on areas with faulty resources. Experimental results have shown that (i) it is possible to generate, place and route the test circuits needed to detect on average more than 99 % of the physical wires and on average about 97 % of the programmable interconnection points of an arbitrary large region of the FPGA in a reasonable time and that (ii) it is possible to download and run the whole test suite on the target device without interfering with the normal functioning of the system

Algebraic and Combinatorial Methods in Computational Complexity

At its core, much of Computational Complexity is concerned with combinatorial objects and structures. But it has often proven true that the best way to prove things about these combinatorial objects is by establishing a connection (perhaps approximate) to a more well-behaved algebraic setting. Indeed, many of the deepest and most powerful results in Computational Complexity rely on algebraic proof techniques. The PCP characterization of NP and the Agrawal-Kayal-Saxena polynomial-time primality test are two prominent examples. Recently, there have been some works going in the opposite direction, giving alternative combinatorial proofs for results that were originally proved algebraically. These alternative proofs can yield important improvements because they are closer to the underlying problems and avoid the losses in passing to the algebraic setting. A prominent example is Dinur's proof of the PCP Theorem via gap amplification which yielded short PCPs with only a polylogarithmic length blowup (which had been the focus of significant research effort up to that point). We see here (and in a number of recent works) an exciting interplay between algebraic and combinatorial techniques. This seminar aims to capitalize on recent progress and bring together researchers who are using a diverse array of algebraic and combinatorial methods in a variety of settings

Why Is It So Difficult to Beat the Random Walk Forecast of Exchange Rates?

We propose a stylized exchange rate model based on diversity and weight of opinion. Our model departs from standard assumptions in that we allow for heterogeneous agents. We show that such a model can explain both the observed volatility and the persistence of real and nominal exchange rate movements and thus in some measure resolves Rogoff’s (1996) purchasing power parity puzzle. Our empirical analysis reconciles the well-known difficulties in beating the random walk forecast model with the statistical evidence of nonlinear mean reversion in deviations from fundamentals. We find strong evidence of long-horizon predictability both in theory and in practice. We also explain why it is difficult to exploit this predictability in out-ofsample forecasts. Our results not only lend support to economists’ beliefs that the exchange rate is inherently predictable, but they also help us to understand the reluctance of applied forecasters to abandon chartists methods in favor of models based on economic fundamentals.Purchasing power parity, Real exchange rate, Random walk, Economic models of exchange rate determination, Long-horizon regression tests.