7,171 research outputs found
Weighted p-bits for FPGA implementation of probabilistic circuits
Probabilistic spin logic (PSL) is a recently proposed computing paradigm
based on unstable stochastic units called probabilistic bits (p-bits) that can
be correlated to form probabilistic circuits (p-circuits). These p-circuits can
be used to solve problems of optimization, inference and also to implement
precise Boolean functions in an "inverted" mode, where a given Boolean circuit
can operate in reverse to find the input combinations that are consistent with
a given output. In this paper we present a scalable FPGA implementation of such
invertible p-circuits. We implement a "weighted" p-bit that combines stochastic
units with localized memory structures. We also present a generalized tile of
weighted p-bits to which a large class of problems beyond invertible Boolean
logic can be mapped, and how invertibility can be applied to interesting
problems such as the NP-complete Subset Sum Problem by solving a small instance
of this problem in hardware
A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs
Crosstalk computing, involving engineered interference between nanoscale
metal lines, offers a fresh perspective to scaling through co-existence with
CMOS. Through capacitive manipulations and innovative circuit style, not only
primitive gates can be implemented, but custom logic cells such as an Adder,
Subtractor can be implemented with huge gains. Our simulations show over 5x
density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper
introduces the Crosstalk circuit style and a key method for large-scale circuit
synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS
synthesis flow by adding two extra steps: conversion of the gate-level netlist
to Crosstalk implementation friendly netlist through logic simplification and
Crosstalk gate mapping, and the inclusion of custom cell libraries for
automated placement and layout. Our logic simplification approach first
converts Cadence generated structured netlist to Boolean expressions and then
uses the majority synthesis tool to obtain majority functions, which is further
used to simplify functions for Crosstalk friendly implementations. We compare
our approach of logic simplification to that of CMOS and majority logic-based
approaches. Crosstalk circuits share some similarities to majority synthesis
that are typically applied to Quantum Cellular Automata technology. However,
our investigation shows that by closely following Crosstalk's core circuit
styles, most benefits can be achieved. In the best case, our approach shows 36%
density improvements over majority synthesis for MCNC benchmark
Technology Mapping for Circuit Optimization Using Content-Addressable Memory
The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This thesis describes a methodology for area-minimizing technology mapping for combinational logic, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual string representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using both exact and inexact string matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization---a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS'85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area reduction shown by LURU is, on average, 20% better compared to FlowMap and CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap
Minimization of Quantum Circuits using Quantum Operator Forms
In this paper we present a method for minimizing reversible quantum circuits
using the Quantum Operator Form (QOF); a new representation of quantum circuit
and of quantum-realized reversible circuits based on the CNOT, CV and
CV quantum gates. The proposed form is a quantum extension to the
well known Reed-Muller but unlike the Reed-Muller form, the QOF allows the
usage of different quantum gates. Therefore QOF permits minimization of quantum
circuits by using properties of different gates than only the multi-control
Toffoli gates. We introduce a set of minimization rules and a pseudo-algorithm
that can be used to design circuits with the CNOT, CV and CV quantum
gates. We show how the QOF can be used to minimize reversible quantum circuits
and how the rules allow to obtain exact realizations using the above mentioned
quantum gates.Comment: 11 pages, 14 figures, Proceedings of the ULSI Workshop 2012 (@ISMVL
2012
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