Open source microprocessor and on-chip-bus for system-on-chip

A System-On-Chip (SoC) is a complex integrated circuit that combines blocks of processor, memory and peripheral devices in one chip. SoCs often form the main or the only component of embedded systems. The advantages of the SoC include improvements in performance, size, reliability, power dissipation, cost, and design turn-around time. The hardware blocks – sometimes referred to as intellectual property cores or just IPs – are connected using a proprietary or open on-chip bus (OCB). The SoCs may be fabricated as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). The non-recurring engineering (NRE) costs for ASICs are much higher although the unit cost for the finished product is lower. For simpler designs and/or lower production runs, FPGAs are usually more cost-effective. One of the costs in implementing an SoC is acquiring the source code or designing the required cores. An approach for reducing costs is to use open source hardware. Open source cores have the advantages of zero license and royalty cost, ability to modify the cores at will, no limitation on supply and maintenance, portability and simplified prototyping. We discuss our implementation of a skeleton SoC incorporating a DLX processor, the Wishbone on-chip bus, and a memory system. The processor bus- memory combination forms a foundation to which a designer can add more cores such as memory and peripherals as long as they comply with the Wishbone protocol. The DLX processor and memory are described in VHDL, while the Wishbone module is in Verilog HDL. Quartus II software is used to synthesize, compile and verify the functionality of CPU and Wishbone by simulation and timing analysis. The partial SoC system is implemented in Altera APEX20KE200 FPGA board. Nios, which is the core processor in the FPGA board, is used as an intermediate processor which communicates with DLX and the rest of the system via Avalon Bus Protocol to verify system operation and functionality in real hardware environment

ANALYSIS OF DISCRETE WAVELET TRANSFORM FOR OPTIMUM MACHINE INSTRUCTION OF DLX MICROPROCESSOR

The application of monitoring over Wireless Sensor Network (WSN) is highly demanded to be implemented in the Internet of Things (IoT). The problem that appears in IoT is the general purpose microprocessor is still highly used, which causes more energy used than it is needed. Although, an Application Specific Integrated Circuit (ASIC) can be used to make a more efficient energy application, it is more expensive and permanent, which means it can\u27t be changed or reconfigured. This thesis presents a method to design a specific purpose microprocessor by compressing an image in DLX microprocessor, which can still be reconfigured by optimizing machine instruction needed in the microprocessor. Prior to DWT process, an image will go through pre-processing stage. The stage will be done in Matlab to turn an RGB image into a grayscale image, and the matrix of the grayscale image will be obtained. This matrix will be the input for Haar DWT machine instruction. The machine instruction is simulated in WinDLX, a simulator for DLX microprocessor. After the simulation has finished, the statistics of the simulation will be analyzed to conclude whether the machine instruction is optimum enough. The result of Haar DWT machine instruction is the same as the result obtained from Matlab, which means the machine instruction is capable to do the image compression. Out of 92 kinds of instruction, Haar machine instruction only needs 20 kinds of instructions used. This shows that the program will not waste energy for unused instruction. From the statistics obtained, the total cycles executed from the pipelined DLX microprocessor is 1239 cycles, where a non-pipelined microprocessor would need 2755 cycles to execute the program. This means the program is a more efficient method to run a Haar DWT compression

A BiCMOS current carrier transceiver on low voltage power lines

This paper presents a BiCMOS technology project of a Current Carrier Transceiver (CCT) for data and digital broadcasting on Low Voltage (LV) power lines (230-240~Vac). The CCT is the central piece in using the LV power lines network as communication channel for various "intelligent" sensors, actuators, monitors, and remote control for domotic or industrial purpose

A BiCMOS current carrier transceiver on low voltage power lines

This paper presents a BiCMOS technology project of a Current Carrier Transceiver (CCT) for data and digital broadcasting on Low Voltage (LV) power lines (230-240~Vac). The CCT is the central piece in using the LV power lines network as communication channel for various "intelligent" sensors, actuators, monitors, and remote control for domotic or industrial purpose

ASAver.1: An FPGA-based education board for computer architecture/system design

Abstract| This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a pipelined RISC processor within limited time available for the course. The approach consists of 4 steps; at the rst step, modeling of pipelined RISC processor is simplied by avoiding structural hazard and by ignoring other hazards, and in the succeeding steps, students learn diculties of pipelining by themselves. An educational FPGA board ASAver.1 and results of feasibility study are also shown

Abstract State Machines 1988-1998: Commented ASM Bibliography

An annotated bibliography of papers which deal with or use Abstract State Machines (ASMs), as of January 1998.Comment: Also maintained as a BibTeX file at http://www.eecs.umich.edu/gasm

Noise Suppression in Images by Median Filter

A new and efficient algorithm for high-density salt and pepper noise removal in images and videos is proposed. In the transmission of images over channels, images are corrupted by salt and pepper noise, due to faulty communications. Salt and Pepper noise is also referred to as Impulse noise. The objective of filtering is to remove the impulses so that the noise free image is fully recovered with minimum signal distortion. Noise removal can be achieved, by using a number of existing linear filtering techniques. We will deal with the images corrupted by salt-and-pepper noise in which the noisy pixels can take only the maximum or minimum values (i.e. 0 or 255 for 8-bit grayscale images)

Hardware-Software Cosynthesis for Digital Systems

As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique problems. The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. System functionality is captured using the HardwareC hardware description language. The synthesis of an Ethernet-based network coprocessor is discussed as an example

Visualization tool for computer architects

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaves 54-55).As computer architectures continue to grow in complexity, software developers and hardware engineers cope with the increasing complexity by developing proprietary applications, simulations and tool sets to understand the behavior of these complex systems. Although the field of information visualization is leading to powerful applications in many areas, information visualization applications for computer architecture development are either tightly coupled with a specific architecture or target a wide range of computer system data. This thesis introduces the Visualization Tool for Computer Architects (VISTA) Environment. The VISTA Environment is an extensible and modular information visualization environment for hardware engineers, software developers and educators to visualize data from a variety of computer architecture simulations at different levels of abstraction. The VISTA Environment leverages common attributes in simulation data, computer architecture visualizations, and computer architecture development methods to create a powerful information visualization environment to aid in designing, understanding and communicating complex computer architectures.by Aaron D. Mihalik.M.Eng