Design and Performance Analysis of a Non-Standard EPICS Fast Controller

The large scientific projects present new technological challenges, such as the distributed control over a communication network. In particular, the middleware EPICS is the most extended communication standard in particle accelerators. The integration of modern control architectures in these EPICS networks is becoming common, as for example for the PXI/PXIe and xTCA hardware alternatives. In this work, a different integration procedure for PXIe real time controllers from National Instruments is proposed, using LabVIEW as the design tool. This methodology is considered and its performance is analyzed by means of a set of laboratory experiments. This control architecture is proposed for achieving the implementation requirements of the fast controllers, which need an important amount of computational power and signal processing capability, with a tight real-time demand. The present work studies the advantages and drawbacks of this methodology and presents its comprehensive evaluation by means of a laboratory test bench, designed for the application of systematic tests. These tests compare the proposed fast controller performance with a similar system implemented using an standard EPICS IOC provided by the CODAC system.Comment: This is the extended version of the Conference Record presented in the IEEE Real-Time Conference 2014, Nara, Japan. This paper has been submitted to the IEEE Transactions on Nuclear Scienc

Time synchronization for an emulated CAN device on a Multi-Processor System on Chip

The increasing number of applications implemented on modern vehicles leads to the use of multi-core platforms in the automotive field. As the number of I/O interfaces offered by these platforms is typically lower than the number of integrated applications, a solution is needed to provide access to the peripherals, such as the Controller Area Network (CAN), to all applications. Emulation and virtualization can be used to implement and share a CAN bus among multiple applications. Furthermore, cyber-physical automotive applications often require time synchronization. A time synchronization protocol on CAN has been recently introduced by AUTOSAR. In this article we present how multiple applications can share a CAN port, which can be on the local processor tile or on a remote tile. Each application can access a local time base, synchronized over CAN, using the AUTOSAR Application Programming Interface (API). We evaluate our approach with four emulation and virtualization examples, trading the number of applications per core with the speed of the software emulated CAN bus.</p

Effect of overmolding process on the integrity of electronic circuits

Traditional injection molding processes have been widely used in the plastic processing industry. It is the major processing technique for converting thermoplastic polymers into complicated 3D parts with the aid of heat and pressure. Next generation of electronic circuits used in different application areas such as automotive, home appliances and medical devices will embed various electronic functionalities in plastic products. In this study, over-molding injection molding (OVM) of electronic components will be examined to insert novel performance in polymer materials. This low-cost manufacturing process offers potential benefits such as, reduction in processing time, higher freedom of design and less energy used when compared to the conventional injection molding method. This paper aims to evaluate the performance of this process and propose a series of alternative solutions to optimize the adhesion between and integration of electronics and engineering plastics. A number of methods are used to optimize the process so that the electronic circuits are not damaged during the over-molding, moreover to test the reliability of the system in order to control the continuity of connections between the electronic circuit foils and the electronic components after the OVM process. Correspondingly, we have performed specific tests for this purpose varying in some conditions: the type of injected plastic used, over-molding parameters (temperature, pressure and injection time), electronic circuit design, type of assembled electronic components, type of foils used and the effect of using underfill material below the electronic component. From these tests, first conclusions were made. We have also studied adhesion between the foil and the over-molding material. In this case, various types of engineering plastics have been tested; polypropylene (PP), 30% weight percentage glass,fiber filled polypropylene (GF-PP), Polyamide-6 (PA6) and 50% weight percentage glass fiber filled polyamide-6 (GF-PA6). It was proved that throughout the wide range of tested materials, (PA6) over-molded samples showed a better adhesion on the copper-polyimide foils than the rest. These plastics were over-molded on two types of polyimide (PP/Copper (Cu) tracks foils with and without an adhesive layer between PI and Cu. It was obviously clear that the foils with on adhesive layer between PI and Cu had more delamination in the Cu tracks than the foils without an adhesive layer. Furthermore, it was shown that the presence of an underfill material has on effect on the system as the foils that had an underfill material below their components successfully had a better connection than the folis without an underfill material. Finally, experiments were executed using the two probe method as an electrical measurement and microscope investigation as the visual inspection

TechNews digests: Jan - Nov 2009

TechNews is a technology, news and analysis service aimed at anyone in the education sector keen to stay informed about technology developments, trends and issues. TechNews focuses on emerging technologies and other technology news. TechNews service : digests september 2004 till May 2010 Analysis pieces and News combined publish every 2 to 3 month

Next generation satellite orbital control system

Selection of the correct software architecture is vital for building successful software-intensive systems. Its realization requires important decisions about the organization of the system and by and large permits or prevents a system\u27s acceptance and quality attributes such as performance and reliability. The correct architecture is essential for program success while the wrong one is a formula for disaster. In this investigation, potential software architectures for the Next Generation Satellite Orbital Control System (NG-SOCS) are developed from compiled system specifications and a review of existing technologies. From the developed architectures, the recommended architecture is selected based on real-world considerations that face corporations today, including maximizing code reuse, mitigation of project risks and the alignment of the solution with business objectives

Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

Deterministic Java in tiny embedded systems

As embedded systems become more and more complex, and the time to market becomes shorter, there is a need in the embedded systems community to find better programming languages that let the programmers develop correct code faster. The programming languages used today, typically C and/or Assemblers, are just too error-prone. The Java technology has therefore gained a lot of interest from developers of embedded systems in the last few years. We propose an approach based on compiling Java into native machine code via C as an intermediate language. The C code generation process should also add close interaction with a fully pre-emptive incremental garbage collector and a small and efficient real time kernel. Tests performed on a small 8-bit microprocessor show that it is possible to use a modern object oriented language with automatic memory management, such as Java, and yet generate fully predictable code that can be run in very small devices with severe memory constraints

An Early-Stage Statement-Level Metric for Energy Characterization of Embedded Processors

Abstract This work presents an early stage statement-level metric for energy characterization of embedded processors. Definition and the framework for metric evaluation are provided. In particular, such a metric is based on an existing assembly-level analysis and some profiling activities performed on a given C benchmark, and it is related to the average energy consumption of a generic C statement, for a given target processor. Its evaluation is performed with a one-time effort and, once available, it can be used to rapidly estimate the energy consumption of a given C function for all the considered processors. Two reference embedded processors are then considered in order to show an example of usage of the proposed metric and framework

Service Level Agreement Driven Adaptive Resource Management For Web Applications on Heterogeneous Compute Clouds

Cloud computing is an emerging topic in the field of parallel and distributed computing. Many IT giants such as IBM, Sun, Amazon, Google, and Microsoft are promoting and offering various storage and compute clouds. Clouds provide services such as high performance computing, storage, and application hosting. Cloud providers are expected to ensure Quality of Service (QoS) through a Service Level Agreement (SLA) between the provider and the consumer. In this research, I develop a heterogeneous testbed compute cloud and investigate adaptive management of resources for Web applications to satisfy a SLA that enforces specific response time requirements. I develop a system on top of EUCALYTPUS framework that actively monitors the response time of the compute resources assign to a Web application and dynamically allocates the resources required by the application to satisfy the specific response time requirements