STRAINTRONIC NANOMAGNETIC DEVICES FOR NON-BOOLEAN COMPUTING

Nanomagnetic devices have been projected as an alternative to transistor-based switching devices due to their non-volatility and potentially superior energy-efficiency. The energy efficiency is enhanced by the use of straintronics which involves the application of a voltage to a piezoelectric layer to generate a strain which is ultimately transferred to an elastically coupled magnetostrictive nanomaget, causing magnetization rotation. The low energy dissipation and non-volatility characteristics make straintronic nanomagnets very attractive for both Boolean and non-Boolean computing applications. There was relatively little research on straintronic switching in devices built with real nanomagnets that invariably have defects and imperfections, or their adaptation to non-Boolean computing, both of which have been studied in this work. Detailed studies of the effects of nanomagnet material fabrication defects and surface roughness variation (found in real nanomagnets) on the switching process and ultimately device performance of those switches have been performed theoretically. The results of these studies place the viability of straintronics logic (Boolean) and/or memory in question. With a view to analog computing and signal processing, analog spin wave based device operation has been evaluated in the presence of defects and it was found that defects impact their performance, which can be a major concern for the spin wave based device community. Additionally, the design challenge for low barrier nanomagnet which is the building block of binary stochastic neurons based probabilistic computing device in case of real nanomagnets has also been investigated. This study also cast some doubt on the efficacy of probabilistic computing devices. Fortunately, there are some non-Boolean applications based on the collective action of array of nanomagnets which are very forgiving of material defects. One example is image processing using dipole coupled nanomagnets which is studied here and it showed promising result for noise correction and edge enhancement of corrupted pixels in an image. Moreover, a single magneto tunnel junction based microwave oscillator was proposed for the first time and theoretical simulations showed that it is capable of better performance compared to traditional microwave oscillators. The experimental part of this work dealt with spin wave modes excited by surface acoustic waves, studied with time resolved magneto optic Kerr effect (TR-MOKE). New hybrid spin wave modes were observed for the first time. An experiment was carried out to emulate simulated annealing in a system of dipole coupled magnetostrictive nanomagnets where strain served as the simulated annealing agent. This was a promising outcome and it is the first demonstration of the hardware variant of simulated annealing of a many body system based on magnetostrictive nanomagnets. Finally, a giant spin Hall effect actuated surface acoustic wave antenna was demonstrated experimentally. This is the first observation of photon to phonon conversion using spin-orbit torque and although the observed conversion efficiency was poor (1%), it opened the pathway for a new acoustic radiator. These studies complement past work done in the area of straintronics

Leveraging Probabilistic Switching in Superparamagnets for Temporal Information Encoding in Neuromorphic Systems

Brain-inspired computing - leveraging neuroscientific principles underpinning the unparalleled efficiency of the brain in solving cognitive tasks - is emerging to be a promising pathway to solve several algorithmic and computational challenges faced by deep learning today. Nonetheless, current research in neuromorphic computing is driven by our well-developed notions of running deep learning algorithms on computing platforms that perform deterministic operations. In this article, we argue that taking a different route of performing temporal information encoding in probabilistic neuromorphic systems may help solve some of the current challenges in the field. The article considers superparamagnetic tunnel junctions as a potential pathway to enable a new generation of brain-inspired computing that combines the facets and associated advantages of two complementary insights from computational neuroscience -- how information is encoded and how computing occurs in the brain. Hardware-algorithm co-design analysis demonstrates $97.41\%$ accuracy of a state-compressed 3-layer spintronics enabled stochastic spiking network on the MNIST dataset with high spiking sparsity due to temporal information encoding

BOOLEAN AND BRAIN-INSPIRED COMPUTING USING SPIN-TRANSFER TORQUE DEVICES

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or ‘spin-neuron’) in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing “human-like” cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching

Dense implementations of binary cellular nonlinear networks : from CMOS to nanotechnology

This thesis deals with the design and hardware realization of the cellular neural/nonlinear network (CNN)-type processors operating on data in the form of black and white (B/W) images. The ultimate goal is to achieve a very compact yet versatile cell structure that would allow for building a network with a very large spatial resolution. It is very important to be able to implement an array with a great number of cells on a single die. Not only it improves the computational power of the processor, but it might be the enabling factor for new applications as well. Larger resolution can be achieved in two ways. First, the cell functionality and operating principles can be tailored to improve the layout compactness. The other option is to use more advanced fabrication technology – either a newer, further downscaled CMOS process or one of the emerging nanotechnologies. It can be beneficial to realize an array processor as two separate parts – one dedicated for gray-scale and the other for B/W image processing, as their designs can be optimized. For instance, an implementation of a CNN dedicated for B/W image processing can be significantly simplified. When working with binary images only, all coefficients in the template matrix can also be reduced to binary values. In this thesis, such a binary programming scheme is presented as a means to reduce the cell size as well as to provide the circuits composed of emerging nanodevices with an efficient programmability. Digital programming can be very fast and robust, and leads to very compact coefficient circuits. A test structure of a binary-programmable CNN has been designed and implemented with standard 0.18 µm CMOS technology. A single cell occupies only 155 µm2, which corresponds to a cell density of 6451 cells per square millimeter. A variety of templates have been tested and the measured chip performance is discussed. Since the minimum feature size of modern CMOS devices has already entered the nanometer scale, and the limitations of further scaling are projected to be reached within the next decade or so, more and more interest and research activity is attracted by nanotechnology. Investigation of the quantum physics phenomena and development of new devices and circuit concepts, which would allow to overcome the CMOS limitations, is becoming an increasingly important science. A single-electron tunneling (SET) transistor is one of the most attractive nanodevices. While relying on the Coulomb interactions, these devices can be connected directly with a wire or through a coupling capacitance. To develop suitable structures for implementing the binary programming scheme with capacitive couplings, the CNN cell based on the floating gate MOSFET (FG-MOSFET) has been designed. This approach can be considered as a step towards a programmable cell implementation with nanodevices. Capacitively coupled CNN has been simulated and the presented results confirm the proper operation. Therefore, the same circuit strategies have also been applied to the CNN cell designed for SET technology. The cell has been simulated to work well with the binary programming scheme applied. This versatile structure can be implemented either as a pure SET design or as a SET-FET hybrid. In addition to the designs mentioned above, a number of promising nanodevices and emerging circuit architectures are introduced.reviewe