Programmable photonics : an opportunity for an accessible large-volume PIC ecosystem

We look at the opportunities presented by the new concepts of generic programmable photonic integrated circuits (PIC) to deploy photonics on a larger scale. Programmable PICs consist of waveguide meshes of tunable couplers and phase shifters that can be reconfigured in software to define diverse functions and arbitrary connectivity between the input and output ports. Off-the-shelf programmable PICs can dramatically shorten the development time and deployment costs of new photonic products, as they bypass the design-fabrication cycle of a custom PIC. These chips, which actually consist of an entire technology stack of photonics, electronics packaging and software, can potentially be manufactured cheaper and in larger volumes than application-specific PICs. We look into the technology requirements of these generic programmable PICs and discuss the economy of scale. Finally, we make a qualitative analysis of the possible application spaces where generic programmable PICs can play an enabling role, especially to companies who do not have an in-depth background in PIC technology

Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

Programmable photonic circuits

[EN] The growing maturity of integrated photonic technology makes it possible to build increasingly large and complex photonic circuits on the surface of a chip. Today, most of these circuits are designed for a specific application, but the increase in complexity has introduced a generation of photonic circuits that can be programmed using software for a wide variety of functions through a mesh of on-chip waveguides, tunable beam couplers and optical phase shifters. Here we discuss the state of this emerging technology, including recent developments in photonic building blocks and circuit architectures, as well as electronic control and programming strategies. We cover possible applications in linear matrix operations, quantum information processing and microwave photonics, and examine how these generic chips can accelerate the development of future photonic circuits by providing a higher-level platform for prototyping novel optical functionalities without the need for custom chip fabricationBogaerts, W.; Pérez-López, D.; Capmany Francoy, J.; Miller, DAB.; Poon, J.; Englund, D.; Morichetti, F.... (2020). Programmable photonic circuits. Nature. 586(7828):207-216. https://doi.org/10.1038/s41586-020-2764-0S2072165867828Chen, X. et al. The emergence of silicon photonics as a flexible technology platform. Proc. IEEE 106, 2101–2116 (2018).Smit, M., Williams, K. & van der Tol, J. Past, present, and future of InP-based photonic integration. APL Photonics 4, 050901 (2019).Capmany, J. & Perez, D. Programmable Integrated Photonics (Oxford Univ. Press, 2020). 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Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform

RÉSUMÉ Les réseaux d’interconnexions programmables (FPIN) se retrouvent largement utilisés dans plusieurs structures bien connues telles que les FPGA, les plateformes de prototypages ainsi que dans plusieurs architectures de réseaux intégrés. Le but de la présente thèse est d’améliorer la structure actuelle des FPIN ainsi que les plateformes de prototypages se basant sur cette technologie afin d’y intégrer d’autres fonctionnalités telles que des interfaces pour les signaux bidirectionnels de type drain-ouvert, les signaux analogiques ou bien les signaux différentiels. Cette thèse présente trois différents circuits qui ont été implémentés dans cette optique. Les interconnexions de ces trois circuits peuvent être reconfigurées pour supporter une interface de type bidirectionnelle drain-ouvert, de type analogique ou différentielle, le tout au travers un réseau d’interconnexions configurable numérique unidirectionnel, ou FPIN. Le besoin d’une telle interface fut tout d’abord envisagé dans le contexte du WaferBoard, qui consiste en une plateforme reconfigurable de prototypage pour les systèmes électroniques. Le cœur de ce WaferBoard consiste en un circuit intégré à l’échelle d’une tranche entière de silicium, qui est constitué d’une matrice bidimensionnelle de cellules. Une large partie de la surface disponible s’en retrouve déjà utilisée par des plots configurables (CIO), l’aiguillage des multiplexeurs du FPIN, des registres dédiés à la chaine JTAG et d’autres circuiteries de contrôle. De ce fait, il en devient primordial que les interfaces bidirectionnelle drain-ouvert, analogique et différentielle soit les plus compactes possibles. Puisque ces circuits d’interfaces seront dédiés pour une plateforme utilisant une tranche de silicium (wafer-scale), l’architecture de ces derniers doit être robuste en regard des variations de procédé, de la température ainsi que de l’alimentation. La première contribution de cette thèse est l’élaboration et la conception d’une interface de type drain-ouvert ainsi que de son support d’interconnexion bidirectionnel utilisant un réseau numérique unidirectionnel à signalisation asymétrique (à l’opposé de la signalisation différentielle) FPIN. L’interface proposée peut interconnecter plusieurs nœuds d’un FPIN. À l’aide de cette interface, le réseau d’interconnexions peut imiter le comportement et le fonctionnement d’un bus de type drain-ouvert (ou collecteur-ouvert) (tel qu’utilisé par le protocole I2C). De ce fait, plusieurs plots de type drain-ouvert provenant d’une multitude de circuits-intégrés (ICs) différents peuvent y être connectés au travers le FPIN à l’aide de l’interface proposée.----------ABSTRACT Field programmable interconnection networks (FPINs) are ubiquitously found embedded in field-programmable gate arrays (FPGAs), in prototyping platforms, and in many Network-on-Chip architectures. The aim of this research was to augment the application domains of current FPIN-based prototyping and emulation platforms by supporting open-drain bi-directional signals, analog signals or differential signals. Three interface circuits have been elaborated and developed to that end in this thesis. These three interface circuits can support reconfigurable routing of open-drain bi-directional, analog and differential signals through an uni-directional digital FPIN. The need for such interface circuits were originally conceived in the context of the WaferBoard, a system prototyping platform. The core of the WaferBoard is a wafer-scale IC that is composed of a two dimensional array of unit cells. Available area was already over-utilized by the configurable I/O (CIO) buffers, crossbar multiplexers of the FPIN, registers of the JTAG chain, and other control circuits. Thus, the interface circuits for open-drain bi-directional, analog and differential signaling had to be made very compact. As the implementation of these interface circuits target “wafer-scale” integration, these interface circuits had to be very robust to parametric variations (process, temperature, power supply). The first contribution of this thesis is the elaboration and development of an open-drain interface circuit and a corresponding interconnect topology to support bi-directional communication through the uni-directional digital FPIN of prototyping platforms. The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavior of open-drain (or open-collector) buses (e.g., those following the I2C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 µm CMOS technology takes 65 µm × 22 µm per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology

Design and prototyping of a network-enabled low-cost low-power seismic sensor monitoring system

Esta tese explora recentes desenvolvimentos em tecnologias de informação, comunicações e sensores no campo da sismologia. A tese aborda o potencial das redes de monitorização sísmica de elevada densidade na melhoria da resolução da actividade sísmica observada e, consequentemente, na melhor compreensão dos processos físicos que estão na base da ocorrência de terramotos. A tese argumenta que a tecnologia de sistemas de microelectromecânica (MEMS), usada na produção de acelerómetros de pequena dimensão, tem aplicabilidade e elevado potencial no domínio da sismologia. Acelerómetros MEMS já facilitaram a instalação de redes sísmicas de elevada densidade com superior resolução espacial pela Universidade da Califórnia (Rede Sísmica Comunitária) e pela Universidade de Évora (Rede Sísmica de Sensores do Alentejo), esta última ainda em fase de instalação. Neste contexto, a tese descreve o trabalho conduzido no desenho e desenvolvimento de sistemas de sensores baseados em acelerómetros MEMS. Este trabalho inclui a conceptualização de componentes de arquitectura usados para a implementação de quatro protótipos. Adicionalmente, foram também desenvolvidos os componentes necessários para a operação e gestão da rede de sensores, que inclui servidores dedicados a operar software especificamente desenvolvido neste trabalho. A tese descreve também a instalação e avaliação de protótipos, usando como base de comparação uma estação sísmica de elevado desempenho, recorrendo inclusivamente à actividade sísmica resultante de dois eventos sísmicos. A tese conclui que a arquitectura conceptualizada para o sistema sensor e para a rede de sensores demonstrou ser eficaz. Adicionalmente, embora a tecnologia MEMS seja promissora, ainda exibe limitações que limitam a sua aplicabilidade no domínio da sismologia, especificamente na observação de eventos sísmicos moderados e fortes. Conclui-se também que a instalação de acelerómetros MEMS em conjunto com sismómetros pode trazer benefícios na observação de actividade sísmica. Espera-se também que futuras gerações de acelerómetros MEMS possam ter uma adoção generalizada na sismologia; ABSTRACT: This thesis exploits advances in information technologies, communications and sensor systems to the field of seismology. It addresses the potential for high-density networks for seismic monitoring aiming to improve the resolution of the recorded seismic activity and, consequently, to improve the understanding of the physical processes that cause earthquakes, as well as to gather more detailed seismic characterisation of studied regions. It argues that microelectromechanical systems (MEMS) technology, used to produce small size accelerometers, has a potential application in seismology. Indeed, MEMS accelerometers have enabled the deployment of high-density seismic networks capable of monitoring seismic activity with high spatial resolution, such as CalTech's Community Seismic Network (CSN) and University of Évora’s SSN-Alentejo, currently in the deployment phase. In this context, this thesis describes the work conducted to design and develop low-cost seismic sensor systems, based on low-cost MEMS accelerometers. This work includes the conceptualisation of the architectural components that were implemented in four prototypes. Moreover, server-side components, necessary to operate and manage the sensor network, as well as to provide visualisation tools for users, are also developed and presented. This work also describes the field deployment and evaluation of selected prototypes, using a high-performance seismic station as the reference sensor for comparison, based on generated signals and two recorded seismic events. It is concluded that the herein conceptualised architecture for the high-dense network and sensor prototypes has been demonstrated to be effective. Moreover, albeit promising, MEMS accelerometers still exhibit performance limitations constraining their application in seismology addressing moderate and strong motion. In addition, MEMS accelerometers characteristics complement seismometers, thus installing MEMS accelerometers with seismometers, may provide additional insights concerning seismic activity and seismology in general. It is also expected that next generation MEMS accelerometers will be capable to compete with traditional seismometers, becoming the de facto technology in seismology

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

Conception d'un réseau de plots configurables multifonctions analogiques et numériques combiné à un réseau de distribution de puissance intégrés à l'échelle de la tranche de silicium

RÉSUMÉ De nos jours, les systèmes électroniques sont en constante croissance en taille et en complexité. Cette complexité combinée à la réduction du temps de mise en marché rendant le design de systèmes électroniques un grand défi pour les designers. Une plateforme de prototypage a récemment été introduite afin de s’attaquer toutes ces contraintes à la fois. Cette plateforme s’appuie sur l’implémentation d’un circuit configurable à l’échelle d’une tranche de silicium complète de 200mm de diamètre. Cette surface est recouverte d’une mer de plots conducteurs configurables appelés NanoPads. Ces NanoPads sont suffisamment petits pour supporter des billes d’un diamètre de 250 μm et d’un espacement de 500 μm et sont regroupés en matrices de 4×4 pour former des Cellules, qui sont à leur tour assemblées en Réticules de 32×32. Ces Réticules sont ensuite photo-répétés sur toute la surface d’une tranche de silicium et sont interconnectés entre eux pour former le WaferIC. Cet arrangement particulier de plots conducteurs configurables permet à un usager de déposer sur la surface active du WaferIC les circuits intégrés constituant un système électronique, sans tenir en compte l’orientation spatiale de ces derniers, de créer un schéma d’interconnexions, de distribution la puissance et de débuter le prototypage du système en question. Une version préliminaire a été fabriquées et testées avec succès et permet d’alimenter des circuits -intégrés et de configurer le WaferIC pour les interconnecter. Cette thèse par articles présente une nouvelle version du WaferIC avec une nouvelle proposition de distribution de la puissance avec une approche de maîtres-esclaves qui met en valeur l’utilisation de plusieurs rails d’alimentation afin d’améliorer le rendement énergétique. Il est également mis de l’avant un réseau très dense de convertisseurs analogique-numérique (CAN) et numérique-analogique (CNA) de plus de 300k éléments, tolérant aux défectuosités et aux défauts de fabrication. Ce réseau de CAN-CNA permet d’améliorer le WaferIC avec la transmission de signaux analogiques, en plus des signaux numériques. Ce manuscrit comporte trois articles : un publié chez « Springer Science & Business Media Analog Integrated Circuits and Signal Processing », un publié chez « IEEE Transactions on Circuits and Systems I : Regular Papers » et finalement un soumis chez « IEEE Transactions on Very Large Scale Integration ».----------ABSTRACT Nowadays, electronic systems are in constant growth, size and complexity; combined with time to market it makes a challenge for electronic system designers. A prototyping platform has been recently introduced and addresses all those constraints at once. This platform is based on an active 200 mm in diameter wafer-scale circuit, which is covered with a set of small configurable and conductive pads called NanoPads. These NanoPads are designed to be small enough to support any integrated-circuit μball of a 250 μm diameter and 500 μm of pitch. They are assembled in a 4×4 matrix, forming a Unit-Cell, which are grouped in a Reticle-Image of 32×32. These Reticle-Images are photo-repeated over the entire surface of a 200 mm in diameter wafer and are interconnected together using interreticle stitching. This active wafer-scale circuit is called a WaferIC. This particular topology and distribution of NanoPads allows an electronic system designer to manually deposit any integrated-circuit (IC) on the active alignment insensitive surface of the WaferIC, to build the netlist linking all the ICs, power-up the systems and start the prototyping of the system. In this manuscript-based thesis, we present an improved version of the WaferIC with a novel approach for the power distribution network with a master-slave topology, which makes the use of embedded dual-power-rail voltage regulators in order to improve the power efficiency and decrease thermal dissipation. We also propose a default-tolerant network of analog to digital (ADC) and digital to analog (DAC) converters of more than 300k. This ADC-DAC network allows the WaferIC to not only support digital ICs but also propagate analog signals from one NanoPad to another. This thesis includes 3 papers : one submission to "Springer Science & Business Media Analog Integrated Circuits and Signal Processing", one submission to "IEEE Transactions on Circuits and Systems I : Regular Papers" and finally one submission to "IEEE Transactions on Very Large-Scale Integration". These papers propose novel architectures of dualrail voltage regulators, configurable analog buffers and configurable voltage references, which can be used as a DAC. A novel approach for a power distribution network and the integration of all the presented architectures is also proposed with the fabrication of a testchip in CMOS 0.18 μm technology, which is a small-scale version of the WaferIC