QR factorization equalisation scheme for mode devision multiplexing transmission in fibre optics

Optical communication systems play a major role in handling worldwide Internet traffic. Internet traffic has been increasing at a dramatic rate and the current optical network infrastructure may not be able to support the traffic growth in a few decades. Mode division multiplexing is introduced as a new emerging technique to improve the optical network capacity by the use of the light modes as individual channels. One of the main issues in MDM is mode coupling which is a physical phenomenon when light modes exchange their energy between each other during propagation through optical fiber resulting in inter-symbol interference (ISI). Many studies based on Least Mean Square (LMS) and Recursive Least Square (RLS) have taken place to mitigate the mode coupling effect. Still, most approaches have high computational complexity and hinders high-speed communication systems. Blind equalisation approach does not need training signals, thus, will reduce the overhead payload. On the other hand, QR factorization shows low computational complexity in the previous research in the radio domain. The combination of these two concepts shows significant results, as the use of low complexity algorithms reduces the processing needed to be done by the communication equipment, resulting in more cost effective and smaller equipment, while having no training signal saves the bandwidth and enhances the overall system performance. To the best knowledge of the researcher, blind equalisation based on QR factorization technique has been not used in MDM equalisation to date. The research goes through the four stages of the design research methodology (DRM) to achieve the purpose of the study. The implementation stage is taken two different simulators has been used, the first one which is the optical simulator is used to collect the initial optical data then, MATLAB is used to develop the equalisation scheme. The development starts with the derivation of the system’s transfer function (H) to be used as the input to the developed equalizer. Blind equalisation based on QR factorization is chosen as a way to introduce an efficient equalization to mitigate ISI by narrowing the pulse width. The development stages include a stage where the channel estimation is taken place. Statistical properties based on the standard deviation (STD) of the powers of the input and output signals has been used for the blind equalisation’s channel estimation part. The proposed channel estimation way has the ability in estimating the channel with an overall mean square error (MSE) of 0.176588301 from the initial transmitted signal. It is found that the worst channel has an MSE of 0.771365 from the transmitted signal, while the best channel has and MSE of 0.000185 from the transmitted signal. This is done by trying to avoid the issues accompanied with the development of the previous algorithms that have been utilized for the same goal. The algorithm mentioned in the study reduces the computational complexity problem which is one of the main issues that accompany currently used tap filter algorithms, such as (LMS) and (RLS). The results from this study show that the developed equalisation scheme has a complexity of O(N) compared with O(N2) for RLS and at the same time, it is faster than LMS as its calculation CPU time is equal to 0.005242 seconds compared with 0.0077814 seconds of LMS. The results are only valid for invertible and square channel matrices

Physical-Layer Cooperation in Coded OFDM Relaying Systems

Mobile communication systems nowadays require ever-increasing data rate and coverage of wide areas. One promising approach to achieve this goal is the application of cooperative communications enabled by introducing intermediate nodes known as relays to support the transmission between terminals. By processing and forwarding the receive message at the relays, the path-loss effect between the source and the destination is mitigated. One major limit factor for relay assisted communications is that a relay cannot transmit and receive using the same physical resources. Therefore, a half-duplex constraint is commonly assumed resulting in halved spectral efficiency. To combat this drawback, two-way relaying is introduced, where two sources exchange information with each. On the other hand, due to the physical limitation of the relays, e.g., wireless sensor nodes, it's not possible to implement multiple antennas at one relay, which prohibits the application of multiple-input multiple-output (MIMO) techniques. However, when treating multiple relays as a cluster, a virtual antenna array is formed to perform MIMO techniques in a distributed manner. %This thesis aims at designing efficient one-way and two-way relaying schemes. Specifically, existing schemes from the literature are improved and new schemes are developed with the emphasis on coded orthogonal frequency division multiplexing (OFDM) transmissions. Of special interest is the application of physical-layer network coding (PLNC) for two-phase two-way relaying. In this case, a network coded message is estimated from the superimposed receive signal at the relay using PLNC schemes. The schemes are investigated based on a mutual information analysis and their performance are improved by a newly proposed phase control strategy. Furthermore, performance degradation due to system asynchrony is mitigated depending on different PLNC schemes. When multiple relays are available, novel cooperation schemes allowing information exchange within the relay cluster are proposed that facilitate distributed MIMO reception and transmission. Additionally, smart signaling approaches are presented to enable the cooperation at different levels with the cooperation overhead taken into account adequately in system performance evaluation

Using reconfigurable computing technology to accelerate matrix decomposition and applications

Matrix decomposition plays an increasingly significant role in many scientific and engineering applications. Among numerous techniques, Singular Value Decomposition (SVD) and Eigenvalue Decomposition (EVD) are widely used as factorization tools to perform Principal Component Analysis for dimensionality reduction and pattern recognition in image processing, text mining and wireless communications, while QR Decomposition (QRD) and sparse LU Decomposition (LUD) are employed to solve the dense or sparse linear system of equations in bioinformatics, power system and computer vision. Matrix decompositions are computationally expensive and their sequential implementations often fail to meet the requirements of many time-sensitive applications. The emergence of reconfigurable computing has provided a flexible and low-cost opportunity to pursue high-performance parallel designs, and the use of FPGAs has shown promise in accelerating this class of computation. In this research, we have proposed and implemented several highly parallel FPGA-based architectures to accelerate matrix decompositions and their applications in data mining and signal processing. Specifically, in this dissertation we describe the following contributions: • We propose an efficient FPGA-based double-precision floating-point architecture for EVD, which can efficiently analyze large-scale matrices. • We implement a floating-point Hestenes-Jacobi architecture for SVD, which is capable of analyzing arbitrary sized matrices. • We introduce a novel deeply pipelined reconfigurable architecture for QRD, which can be dynamically configured to perform either Householder transformation or Givens rotation in a manner that takes advantage of the strengths of each. • We design a configurable architecture for sparse LUD that supports both symmetric and asymmetric sparse matrices with arbitrary sparsity patterns. • By further extending the proposed hardware solution for SVD, we parallelize a popular text mining tool-Latent Semantic Indexing with an FPGA-based architecture. • We present a configurable architecture to accelerate Homotopy l1-minimization, in which the modification of the proposed FPGA architecture for sparse LUD is used at its core to parallelize both Cholesky decomposition and rank-1 update. Our experimental results using an FPGA-based acceleration system indicate the efficiency of our proposed novel architectures, with application and dimension-dependent speedups over an optimized software implementation that range from 1.5ÃÂ to 43.6ÃÂ in terms of computation time