Progress on Carbon Nanotube BEOL Interconnects

This article is a review of the current progress and results obtained in the European H2020 CONNECT project. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, 2) modeling and simulation from atomistic to circuit-level bench-marking and performance prediction, and 3) characterization and electrical measurements. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a review and informative cornerstone on carbon nanotube interconnects

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Copper Metal for Semiconductor Interconnects

Resistance-capacitance (RC) delay produced by the interconnects limits the speed of the integrated circuits from 0.25 mm technology node. Copper (Cu) had been used to replace aluminum (Al) as an interconnecting conductor in order to reduce the resistance. In this chapter, the deposition method of Cu films and the interconnect fabrication with Cu metallization are introduced. The resulting integration and reliability challenges are addressed as well

Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond

The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process parameters, for instance, the interconnect barrier/liner bilayer thickness and aspect ratio, on the design and optimization of a multilevel interconnect network. A framework to perform a sensitivity analysis for the circuit behavior to interconnect process parameters is created for future FinFET CMOS technology nodes. Multiple predictive cell libraries down to the 7‒nm technology node are constructed to enable early investigation of the electronic chip performance using commercial electronic design automation (EDA) tools with real chip information. Findings indicated new opportunities that arise for emerging novel interconnect technologies from the materials and process perspectives. These opportunities are evaluated based on potential benefits that are quantified with rigorous circuit-level simulations and requirements for key parameters are underlined. The impacts of various emerging interconnect technologies on the performances of emerging devices are analyzed to quantify the realistic circuit- and system-level benefits that these new switches can offer.Ph.D

Materials and processes for advanced lithography applications

textStep and Flash Imprint Lithography (S-FIL) is a high resolution, next-generation lithography technique that uses an ambient temperature and low pressure process to replicate high resolution images in a UV-curable liquid material. Application of the S-FIL process in conjunction with multi-level imprint templates and new imprint materials enables one S-FIL step to reproduce the same structures that require two photolithography steps, thereby greatly reducing the number of patterning steps required for the copper, dual damascene process used to fabricate interconnect wirings in modern integrated circuits. Two approaches were explored for the implementation of S-FIL in the dual damascene process: sacrificial imprint materials and imprintable dielectric materials. Sacrificial imprint materials function as a pattern recording medium during S-FIL and a three-dimensional etch mask during the dielectric substrate etch, enabling the simultaneous patterning of both the via and metal structures in the dielectric substrate. Development of sacrificial imprint materials and the associated imprint and etch processes are described. Application of S-FIL and the sacrificial imprint material in a commercial copper dual damascene process successfully produced functional copper interconnect structures, demonstrating the feasibility of integrating multi-level S-FIL in the copper dual damascene process. Imprintable dielectric materials are designed to combine the multi-level patterning capability of S-FIL with novel dielectric precursor materials, enabling the simultaneous deposition and patterning of the interlayer dielectric material. Several candidate imprintable dielectric materials were evaluated: sol-gel, polyhedral oligomeric silsesquioxane (POSS) epoxide, POSS acrylate, POSS azide, and POSS thiol. POSS thiol shows the most promise as functional imprintable dielectric material, although additional work in the POSS thiol formulation and viscous dispense process are needed to produce functional interconnect structures. Integration of S-FIL with imprintable dielectric materials would enable further streamlining of the dual damascene fabrication process. The fabrication of electronic devices on flexible substrates represents an opportunity for the development of macroelectronics such as flexible displays and large area devices. Traditional optical lithography encounters alignment and overlay limitations when applied on flexible substrates. A thermally activated, dual-tone photoresist system and its associated etch process were developed to enable the simultaneous patterning of two device layers on a flexible substrate.Chemical Engineerin

Carbon nanotubes for thermal interface materials in microelectronic packaging

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ~35% and ~65%, respectively, in tensile strength (~0.8 GPa) and modulus (~90 GPa) during tensile testing; an ~20% improvement in electrical conductivity (~80000 S m⁻¹) was also reported. The mechanism of the microwave response of CNTs was discussed. Such an microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ~30 mm² s⁻¹ along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ~27 and ~540 W m⁻¹ K⁻¹, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ~1×10⁻⁷ m² K W⁻¹. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.PhDCommittee Chair: Wong, C. P.; Committee Member: Graham, Samuel; Committee Member: Hess, Dennis; Committee Member: Jacob, Karl; Committee Member: Wang, Z. L.; Committee Member: Yao, Don

TOWARDS INTEGRATION OF GRAPHENE IN ADVANCED CMOS INTERCONNECT TECHNOLOGY

The integration of graphene into existing state-of-the-art semiconductor manufacturing is a topic of worldwide interest. With its unprecedented electrical, thermal and mechanical properties, graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to demonstrate BEOL-compatible graphene growth techniques, and explore various avenues for practical integration of graphene in order to achieve better electrical, thermal and reliability metrics than traditional interconnect technology

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl