12 research outputs found
Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs
Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code
Implementation and Characterisation of Monolithic CMOS Pixel Sensors for the CLIC Vertex and Tracking Detectors
Different CMOS technologies are being considered for the vertex and tracking layers of the detector at the proposed high-energy ee Compact Linear Collider (CLIC). CMOS processes have been proven to be suitable for building high granularity, large area detector systems with low material budget and low power consumption. An effort is put on implementing detectors capable of performing precise timing measurements. Two Application-Specific Integrated Circuits (ASICs) for particle detection have been developed in the framework of this thesis, following the specifications of the CLIC vertex and tracking detectors. The process choice was based on a study of the features of each of the different available technologies and an evaluation of their suitability for each application. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a pixelated detector chip designed to be used in capacitively coupled assemblies with the CLICpix2 readout chip, in the framework of the vertex detector at CLIC. The chip comprises a matrix of 128×128 square pixels with 25 µm pitch. A commercial 180 nm High-Voltage (HV) CMOS process was used for the C3PD design. The charge is collected with a large deep N-well, while each pixel includes a preamplifier placed on top of the collecting electrode. The C3PD chip was produced on wafers with different values for the substrate resistivity (∼ 20, 80, 200 and 1000 Ωcm) and has been extensively tested through laboratory measurements and beam tests. The design details and characterisation results of the C3PD chip will be presented. The CLIC Tracker Detector (CLICTD) is a novel monolithic detector chip developed in the context of the silicon tracker at CLIC. The CLICTD chip combines high density, mixed mode circuits on the same substrate, while it performs a fast time-tagging measurement with 10 ns time bins. The chip is produced in a 180 nm CMOS imaging process with a High-Resistivity (HR) epitaxial layer. A matrix of 16×128 detecting cells, each measuring 300 × 30 µm , is included. A small N-well is used to collect the charge generated in the sensor volume, while an additional deep N-type implant is used to fully deplete the epitaxial layer. Using a process split, additional wafers are produced with a segmented deep N-type implant, a modification that has been simulated to result in a faster charge collection time. Each detecting cell is segmented into eight front-ends to ensure prompt charge collection in the sensor diodes. A simultaneous 8-bit timing and 5-bit energy measurement is performed in each detecting cell. A detailed description of the CLICTD design will be given, followed by the first measurement results
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>Dissertatio
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de
imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da
matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos
de operação, assim como as suas características físicas e suas métricas de avaliação. No
seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem
atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais
do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto
com o possível trabalho futuro
MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS
This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies
Detector Technologies for CLIC
The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear
electron-positron collider under development. It is foreseen to be built and
operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3
TeV, respectively. It offers a rich physics program including direct searches
as well as the probing of new physics through a broad set of precision
measurements of Standard Model processes, particularly in the Higgs-boson and
top-quark sectors. The precision required for such measurements and the
specific conditions imposed by the beam dimensions and time structure put
strict requirements on the detector design and technology. This includes
low-mass vertexing and tracking systems with small cells, highly granular
imaging calorimeters, as well as a precise hit-time resolution and power-pulsed
operation for all subsystems. A conceptual design for the CLIC detector system
was published in 2012. Since then, ambitious R&D programmes for silicon vertex
and tracking detectors, as well as for calorimeters have been pursued within
the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector
requirements with innovative technologies. This report introduces the
experimental environment and detector requirements at CLIC and reviews the
current status and future plans for detector technology R&D.Comment: 152 pages, 116 figures; published as CERN Yellow Report Monograph
Vol. 1/2019; corresponding editors: Dominik Dannheim, Katja Kr\"uger, Aharon
Levy, Andreas N\"urnberg, Eva Sickin
Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process
Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits.
The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated
Miniature high dynamic range time-resolved CMOS SPAD image sensors
Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003,
single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration
quantum-level image sensors. Their unique feature of discerning single photon detections, their ability
to retain temporal information on every collected photon and their amenability to high speed image
sensor architectures makes them prime candidates for low light and time-resolved applications.
From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical
phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications
such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge
steps in detector and sensor architectures have been made to address the design challenges of pixel
sensitivity and functionality trade-off, scalability and handling of large data rates.
The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and
fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved
applications with a small pixel pitch while maintaining both sensitivity and built -in functionality.
Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates
and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing
capability, smarter pixel designs with configurable functionality and novel system architectures that
lift the processing burden off the pixel array and mediate data flow.
Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side
illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process
and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel
pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated
shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS)
achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel
data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first
demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection.
Characterisation results of the detector and sensor performance are presented.
Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a
fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal
plane data processing and storage for high dynamic range as well as autonomous video rate operation.
Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a
highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable
region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram
generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both
architectures are discussed
Topical Workshop on Electronics for Particle Physics
The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities
Full Proceedings, 2018
Full conference proceedings for the 2018 International Building Physics Association Conference hosted at Syracuse University