How co-production underpinned the development of a logic model and testing of novel statistical methods for evidence synthesis

Background: The CEPHI project sought to develop and test four methods for synthesizing evidence that better accounted for context than standard statistical meta-analysis approaches. To explore context, we had to understand what was important in different contexts. We identified co-production as an approach to achieve this. / Methods: Supported by the Co-Production Collective, we worked closely with an Advisory Group of people with lived, professional, and/or academic expertise. We held a series of workshops with others bringing lived, professional, and/or academic expertise, to co-produce a logic model that subsequently informed novel synthesis methods. Evaluation of the co-production element was through reflexive notes, feedback from participants, and discussions during and after the project. / Results: The impact of co-production was profound. It fundamentally redesigned the entire logic model. This enabled novel statistical methods to answer important questions about context and impact. There were emotional impacts (highs and lows) and resource implications. / Discussion: Co-production is a powerful way to develop logic models and to inform synthesis methods development, by focusing on what is important to the affected communities. We will discuss lessons learned, what we would do differently next time, and what might be some of the key conditions and mechanisms for meaningful co-production

From the industrial district to the innovative milieu: Contribution to an analysis of territorialised productive organisations

The interest shown in territorialized productive organizations does not simply account for a geographical phenomenon but above all highlights the territorial dimension of development and innovation processes. In the wake of the work done on Italian industrial districts, numerous studies have been conducted that have made it possible to identify similar forms of localized productive organizations. The aim of the present paper is to attempt a synthesis of the way in which these territorialized productive organizations work. To do so, we shall select two concepts: the localized production system and the milieu. The fundamental question is then to identify which logic influences the way a localized production system works: the milieu-actuated territorial logic or the functional logic, which corresponds to industrial organization of an hierarchical natur

N channel JFET based digital logic gate structure

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

A temporal logic approach to modular design of synthetic biological circuits

We present a new approach for the design of a synthetic biological circuit whose behaviour is specified in terms of signal temporal logic (STL) formulae. We first show how to characterise with STL formulae the input/output behaviour of biological modules miming the classical logical gates (AND, NOT, OR). Hence, we provide the regions of the parameter space for which these specifications are satisfied. Given a STL specification of the target circuit to be designed and the networks of its constituent components, we propose a methodology to constrain the behaviour of each module, then identifying the subset of the parameter space in which those constraints are satisfied, providing also a measure of the robustness for the target circuit design. This approach, which leverages recent results on the quantitative semantics of Signal Temporal Logic, is illustrated by synthesising a biological implementation of an half-adder

Against the Virtual: Kleinherenbrink’s Externality Thesis and Deleuze’s Machine Ontology

Drawing from Arjen Kleinherenbrink's recent book, Against Continuity: Gilles Deleuze's Speculative Realism (2019), this paper undertakes a detailed review of Kleinherenbrink's fourfold "externality thesis" vis-à-vis Deleuze's machine ontology. Reading Deleuze as a philosopher of the actual, this paper renders Deleuzean syntheses as passive contemplations, pulling other (passive) entities into an (active) experience and designating relations as expressed through contraction. In addition to reviewing Kleinherenbrink's book (which argues that the machine ontology is a guiding current that emerges in Deleuze's work after Difference and Repetition) alongside much of Deleuze's oeuvre, we relate and juxtapose Deleuze's machine ontology to positions concerning externality held by a host of speculative realists. Arguing that the machine ontology has its own account of interaction, change, and novelty, we ultimately set to prove that positing an ontological "cut" on behalf of the virtual realm is unwarranted because, unlike the realm of actualities, it is extraneous to the structure of becoming-that is, because it cannot be homogenous, any theory of change vis-à-vis the virtual makes it impossible to explain how and why qualitatively different actualities are produced