Impact of the hardened floating-point cores on HIL technology

The Hardware-In-the-Loop (HIL) technique is increasingly used for testing power electronics. FPGAs (Field-Programmable Gate Array) are becoming usual in this kind of emulation due to their acceleration capabilities. But even using FPGAs, it has not been possible to reach real time simulations when small integration steps are necessary (around 100 ns or lower) if floating-point representation is used. Fixed-point has been the solution, but at a high design effort cost. With the release of FPGAs with HFP (Hardened Floating-Point) cores – dedicated floating-point blocks implemented in silicon – the minimum achievable simulation step decreases significantly. This paper presents a comparison between HFP cores, floating-point in programmable logic and fixed-point for HIL models. Results show that both HFP-based and fixed-point arithmetic achieve a simulation step around 10 ns for a full-bridge converter model. A comparison regarding resolution and accuracy is also presented, because acceleration is not the only issue when decreasing the integration step. Numerical resolution also plays an important role, and 32-bit floating-point representation finds a double barrier: acceleration marked by technology, and numerical resolution. Both are explored in this paperThis work has been supported by the Spanish Ministerio deEconomía y Competitividad under project TEC2013-43017-

Programmable flexible cores for SoC applications

Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200

Embedded processors on FPGA: Hard-core vs Soft-core

Field Programmable Gate Arrays (FPGAs) are integrated circuits (ICs) that can be reprogrammed by the consumer after manufacturing. They are based on a matrix of configurable logic blocks connected via programmable interconnects that enables the designer to quickly recreate hardware circuits. In the past, FPGAs were primarily used for prototyping and debugging purposes. However, with their increased popularity, many commercial products now incorporate FPGAs. In the late 1990s, FPGA vendors introduced System-on-chip (SoC) devices that housed one or more hard-core processors and an FPGA fabric on a single IC to allow for more complex designs that involved hardware and software co-integration. While this approach provides advantages of running your design at much higher speeds it does not provide the flexibility of modification to suit the application. Because of this many FPGA vendors provide the solution of using soft-core processors that are configured from logic resources inside the FPGA. While this approach provides the advantage of flexibility they run at about 30% to 50% of the speed of the hard-core processors. Thus each approach has its own advantages and disadvantages. In this thesis, an application was developed to run on two different FPGA platforms. The first platform, Digilent Zybo FPGA board, houses an ARM-Cortex hard-core while the other, Digilent Nexys-4 board, implemented ARM-Cortex soft-core using FPGA resources. IP blocks were designed in Hardware Description Languages Verilog and VHDL to interface with the processor and it’s supported Bus Architecture (AXI/AHB). The application was written in C and assembly language and enacted the function of a Digital Oscilloscope. It used the ADC ports on the FPGA board to continuously read analog signals and plotted them as a dynamic waveform on a VGA monitor. Xilinx Vivado was the primary IDE used for HDL design, synthesis, simulation and implementation for both the platforms. Reports generated from Vivado as well as the run-time results were used to compare the two platforms and identify their strengths and weaknesses. Also discussed is the methodology for choosing either board over the other