77,544 research outputs found

### Design citeria for applications with non-manifest loops

In the design process of high-throughput applications, design choices concerning the type of processor architecture and appropriate scheduling mechanism, have to be made. Take a reed-solomon decoder as an example, the amount of clock cycles consumed in decoding a code is dependent on the amount of errors within that code. Since this is not known in advance, and the environment in which the code is transmitted can cause a variable amount of errors within that code, a processor architecture which employs a static scheduling scheme, has to assume the worst case amount of clock cycles in order to cope with the worst case situation and provide correct results. On the other hand a processor that employs a dynamic scheduling scheme, can gain wasted clock cycles, by scheduling the exact amount of clock cycles that are needed and not the amount of clock cycles needed for the worst case situation. Since processor architectures that employ dynamic scheduling schemes have more overhead, designers have to make their choice beforehand. In this paper we address the problem of making the correct choice of whether to use a static or dynamic scheduling scheme. The strategy is to determine whether the application possess non-manifest behavior\ud
and weigh out this dynamic behavior against static scheduling solutions which were quite common in the past. We provide criteria for choosing the correct scheduling architecture for a high throughput application based upon the environmental and algorithm-specification constraints. KeywordsÂż Non-manifest loop scheduling, variable latency functional units, dynamic hardware scheduling, self\ud
scheduling hardware units, optimized data-flow machine architecture

### Energy-efficient algorithms for non-preemptive speed-scaling

We improve complexity bounds for energy-efficient speed scheduling problems
for both the single processor and multi-processor cases. Energy conservation
has become a major concern, so revisiting traditional scheduling problems to
take into account the energy consumption has been part of the agenda of the
scheduling community for the past few years.
We consider the energy minimizing speed scaling problem introduced by Yao et
al. where we wish to schedule a set of jobs, each with a release date, deadline
and work volume, on a set of identical processors. The processors may change
speed as a function of time and the energy they consume is the $\alpha$th power
of its speed. The objective is then to find a feasible schedule which minimizes
the total energy used.
We show that in the setting with an arbitrary number of processors where all
work volumes are equal, there is a $2(1+\varepsilon)(5(1+\varepsilon))^{\alpha
-1}\tilde{B}_{\alpha}=O_{\alpha}(1)$ approximation algorithm, where
$\tilde{B}_{\alpha}$ is the generalized Bell number. This is the first constant
factor algorithm for this problem. This algorithm extends to general unequal
processor-dependent work volumes, up to losing a factor of
$(\frac{(1+r)r}{2})^{\alpha}$ in the approximation, where $r$ is the maximum
ratio between two work volumes. We then show this latter problem is APX-hard,
even in the special case when all release dates and deadlines are equal and $r$
is 4.
In the single processor case, we introduce a new linear programming
formulation of speed scaling and prove that its integrality gap is at most
$12^{\alpha -1}$. As a corollary, we obtain a $(12(1+\varepsilon))^{\alpha -1}$
approximation algorithm where there is a single processor, improving on the
previous best bound of $2^{\alpha-1}(1+\varepsilon)^{\alpha}\tilde{B}_{\alpha}$
when $\alpha \ge 25$

### Flexible multi-policy scheduling based on CPU inheritance

Journal ArticleTraditional processor scheduling mechanisms in operating systems are fairly rigid, often supporting only one fixed scheduling policy, or, at most, a few "scheduling classes" whose implementations are closely tied together in the OS kernel. This paper presents CPU inheritance scheduling, a novel processor scheduling framework in which arbitrary threads can act as schedulers for other threads. Widely different scheduling policies can be implemented under the framework, and many different policies can coexist in a single system, providing much greater scheduling flexibility. Modular, hierarchical control can be provided over the processor utilization of arbitrary administrative domains, such as processes, jobs, users, and groups, and the CPU resources consumed can be accounted for and attributed accurately. Applications as well as the OS can implement customized local scheduling policies; the framework ensures that all the different policies work together logically and predictably. As a side effect, the framework also cleanly addresses priority inversion by providing a generalized form of priority inheritance that automatically works within and among multiple diverse scheduling policies. CPU inheritance scheduling extends naturally to multiprocessors, and supports processor management techniques such as processor affinity [7] and scheduler activations [1]. Experimental results and simulations indicate that this framework can be provided with negligible overhead in typical situations, and fairly small (5-10%) performance degradation even in scheduling-intensive situations

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### Percolation scheduling with resource constraints

This paper presents a new approach to resource-constrained compiler extraction of fine-grain parallelism, targeted towards VLIW supercomputers, and in particular, the IBM VLIW (Very Large Instruction Word) processor. The algorithms described integrate resource limitations into Percolation Schedulingâa global parallelization techniqueâto deal with resource constraints, without sacrificing the generality and completeness of Percolation Scheduling in the process. This is in sharp contrast with previous approaches which either applied only to conditional-free code, or drastically limited the parallelization process by imposing relatively local heuristic resource constraints early in the scheduling process

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