The Application of Atomic Force Microscopy in Semiconductor Technology - Towards High-K Gate Dielectric Integration

Development of semiconductor technology over the last five decades has led to aggressive scaling down of integrated circuit (IC) device dimensions. ICs have become faster, denser and more power-efficient by continuous shrinking down of the metal-oxide-semiconductor field-effect transistor (MOSFET) size and implementation of complex integration schemes using novel materials. We are steadily approaching the physical limits of scaling and along the way more and more obstacles appear that need to be overcome in order to continue further. Traditional process control and device characterization techniques are becoming insufficient for addressing these problems. Novel techniques must be implemented for obtaining information about structural and electrical properties on materials and geometries with nanometer resolution. This is particularly relevant at the present transition from silicon dioxide gate dielectrics to ones with higher dielectric permittivity – high-K dielectrics. The present work is a contribution to this search for novel suitable analytical techniques and their implementation in semiconductor technology. It exploits extensively the high resolution imaging possibilities of atomic force microscopy (AFM) as a key support technique from the selection of prospective high-K candidates to their integration into a suitable MOSFET fabrication process. Particular attention is paid to conductive atomic force microscopy (C-AFM) which offers the possibility of mapping simultaneously topography dimensions and electrical conductivity. Initially, AFM and C-AFM are used for the development and optimization of a device isolation technology that is relevant in the context of high-K dielectrics in ultra large scale integration (ULSI) ICs – shallow trench isolation (STI). For the first time, reliable detection is obtained of the common problem related to STI – nitride erosion after the chemical planarization (CMP) step. Again with the help of C-AFM, two different techniques for planarity optimization are developed and evaluated – oxide etchback and reverse nitride masking. Next, C-AFM supports the investigation of two principally different types of prospective high-K dielectric materials. First generation dual-stack dielectrics that consist of a high-K material on top of a thin interfacial silicon dioxide layer are the easier but less effective solution. C-AFM reveals imperfections in the investigated titanium oxide – silicon dioxide stacks related to the insufficient stability of such bilayer structures. Second generation high-K dielectrics in the face of epitaxial rare-earth metal oxides possess key advantages such as higher thermal stability and the possibility for engineered interface with silicon. C-AFM investigates their properties and proves the superiority of these materials. Imperfections are observed as well that show the need for growth and processing optimizations. For the first time, charge trapping is observed on the nanoscale directly on the high-K dielectric surface. Nonuniform leakages in rare-earth metal oxides grown under insufficiently optimized conditions presumably related to grain boundaries are discovered in some samples. Based on AFM measurements, predictions are made about the expected behavior of MOS devices incorporating these materials. The compatibility of epitaxial rare-earth metal oxides with standard complementary metal-oxide-semiconductor (CMOS) processing is investigated next. Incompatibility with some steps such as for example cleaning with acid-containing solutions is determined and suitable replacement steps are chosen. Changes in film properties are determined during key steps that could indicate incompatibility of the dielectrics with the standard gate-first integration scheme. In order to determine to what extent the observed microscopic changes affect macroscopic device behavior, epitaxial dielectric layers are integrated for the first time into complete devices. Rare earth metal oxide MOSFETs are fabricated into a modified gate-first process using different gate dielectrics. C-AFM is used for process control in critical steps. Electrical evaluation of the functional devices featuring praseodymium oxide (Pr2O3), including charge pumping, reveals that at this initial stage of development the high-K gate dielectric devices suffer from degraded performance when compared to SiO2 reference devices. Imperfections such as high density of interface states, susceptibility to charge trapping and gate leakages for large area devices are observed. Neodymium oxide (Nd2O3) integration after further optimization of the gate-first process fails to produce functional devices due to substantial degradation of the gate dielectric and excessive gate leakages. The MOSFET behavior for both materials as determined by macroscopic electrical characterization results is compared to AFM predictions and they coincide very well. It is concluded that the imperfections of the gate dielectrics are at least partially a result of the integration process. Analysis is carried out and critical performance-reducing steps are identified. The gate structuring by reactive ion etch (RIE), the source/drain ion implantation and the high temperature source/drain activation anneal are responsible for the dielectric degradation to the largest extent. The inseparable link between these steps and conventional processing leads to the idea of implementing an entirely different approach for gentle integration of high-K dielectrics. Once again with the help of AFM and C-AFM, a replacement gate technology (RGT) is developed and implemented for high-K gate dielectric MOS devices in order to prove this concept. By positioning the gate dielectric growth module after the source/drain implantation and anneal and avoiding the aggressive RIE through indirect gate patterning with CMP, the integration process is adapted to the sensitive high-K materials in order to preserve their as-grown state. Electrical evaluation of devices with Gd2O3 produced using RGT proves the advantage of RGT. The first integration attempt is compared to conventional fabrication technology and there are definite improvements in terms of threshold voltage stability and interface state distribution. The first RGT high-K devices still do not exhibit the mobility and low defect density of equivalent state-of-the-art SiO2 devices but this is expected considering the 40-year-long optimization history behind silicon dioxide. Further optimization is needed for epitaxial rare-earth metal oxides as well, both in terms of growth conditions and process integration

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

Doped And Chemically Transformed Transition Metal Dichalcogenides (tmdcs) For Two-Dimensional (2d) Electronics

Transition metal dichalcogenides (TMDCs) as the semiconductor counterparts of gra-phene have emerged as promising channel materials for flexible electronic and optoelectronic devices. The 2D layer structure of TMDCs enables the ultimate scaling of TMDC-based devices down to atomic thickness. Furthermore, the absence of dangling bonds in these materials helps to form high quality heterostructures with ultra-clean interfaces. The main objective of this work is to develop novel approaches to fabricating TMDC-based 2D electronic devices such as diodes and transistors. In the first part, we have fabricated 2D p-n junction diodes through van der Waals assembly of heavily p-doped MoS2 (WSe2) and lightly n-doped MoS2 to form vertical homo-(hetero-) junctions, which allows to continuously tune the electron concentration on the n-side for a wide range. In sharp contrast to conventional p-n junction diodes, we have observed nearly exponential dependence of the reverse-current on gate-voltage in our 2D p-n junction devices, which can be attributed to band-to-band tunneling through a gate-tunable tunneling barrier. In the second part, we developed a new strategy to engineer high-κ dielectrics by con-verting atomically thin metallic 2D TMDCs into high-κ dielectrics because it remains a signifi-cant challenge to deposit uniform high-κ dielectric thin films on TMDCs with ALD due to the lack of dangling bonds on the surfaces of TMDCs. In our study, we converted mechanically ex-foliated atomically thin layers of a 2D metal, TaS2 (HfSe2) into a high-κ dielectric, Ta2O5 (HfO2) by thermal oxidation. X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive spectroscopy (EDS), and atomic force microscopy (AFM) were used to understand the phase conversion process. Capacitance-voltage (C-V) measure-ments were carried out to determine the dielectric constant of thermally oxidized dielec-trics. We fabricated MoS2 field-effect transistors (FETs) with thermally oxidized ultra-thin and ultra-smooth Ta2O5 as top-gate and bottom-gate high-κ dielectric layers. We observed promis-ing device performance, including a nearly ideal subthreshold swing of ~ 61 mV/dec at room temperature, negligible hysteresis, drain-current saturation in the output characteristics, a high on/off ratio ~ 106, and a room temperature field-effect mobility exceeding 60 cm2/Vs. To fur-ther reduce the leak current and improve the device performance, we have also investigated the chemical transformation of HfSe2 to HfO2 high-κ dielectric, which has significantly larger band gap than Ta2O5

Solution processed molecular floating gate for flexible flash memories

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

Insulators for 2D nanoelectronics: the gap to bridge

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators

신축성 있고 착용 가능한 탄소 나노튜브 기반 전자 기술

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 협동과정 바이오엔지니어링전공, 2020. 8. 김대형.Networks of carbon nanotubes (CNTs) are a promising candidate for use as a basic building block for next-generation soft electronics, owing to their superior mechanical and electrical properties, chemical stability, and low production cost. In particular, the CNTs, which are produced as a mixture of metallic and semiconducting CNTs via chemical vapor deposition, can be sorted according to their electronic types, which makes them useful for specific purposes: semiconducting CNTs can be employed as channel materials in transistor-based applications and metallic CNTs as electrodes. However, the development of CNT-based electronics for soft applications is still at its infant stage, mainly limited by the lack of solid technologies for developing high-performance deformable devices whose electrical performances are comparable to those fabricated using conventional inorganic materials. In this regard, soft CNT electronics with high mechanical stability and electrical performances have been pursued. First, wearable nonvolatile memory modules and logic gates were fabricated by employing networks of semiconducting CNTs as the channel materials, with strain-tolerant device designs for high mechanical stability. The fabricated devices exhibited low operation voltages, high device-to-device uniformity, on/off ratios, and on-current density, while maintaining its performance during ~30% stretching after being mounted on the human skin. In addition, various functional logic gates verified the fidelity of the reported technology, and successful fabrication of non-volatile memory modules with wearable features has been reported for the first time at the time of publication. Second, the networks of semiconducting CNTs were used to fabricate signal amplifiers with a high gain of ~80, which were then used to amplify electrocardiogram (ECG) signals measured using a wearable sensor. At the same time, color-tunable organic light-emitting diodes (CTOLEDs) were developed based on ultra-thin charge blocking layer that controlled the flow of excitons during different voltage regimes. Together, they were integrated to construct a health monitoring platform whereby real-time ECG signals could be detected while simultaneously notifying its user of the ECG status via color changes of the wearable CTOLEDs. Third, intrinsically stretchable CNT transistors were developed, which was enabled by the developments of thickness controllable, vacuum-deposited stretchable dielectric layer and vacuum-deposited metal thin films. Previous works employed strain-tolerant device designs which are based on the use of filamentary serpentine-shaped interconnections, which severely sacrifice the device density. The developed stretchable dielectric, compatible with the current vacuum-based microfabrication technology, exhibited excellent insulating properties even for nanometer-range thicknesses, thereby enabling significant electrical performance improvements such as low operation voltage and high device uniformity/reproducibility, which has not been realized in the most advanced intrinsically stretchable transistors of today.탄소 나노튜브는 뛰어난 전기적, 화학적, 그리고 기계적 특성을 갖고 있어 차세대 유연 전자소자의 핵심 소재 중 하나로 각광을 받고 있으나, 아직까지 이를 이용한 실용적인 유연 전자소자의 개발은 실현되지 않고 있다. 이는 탄소 나노튜브의 전기적 특성대로 완벽히 분류해 낼 수 있는 기술, 탄소 나노튜브를 소자의 원하는 위치에 정확히 원하는 양만큼 네트워크 형태 혹은 정렬된 형태로 증착하는 기술, 그리고 유연 전자소자를 구성하는 다른 물질들의 개발 기술의 부재 때문이다. 지난 10여년간 해당 기술들은 광범위하게 연구되어지고 있으나, 탄소 나노튜브를 활용한 우수한 유연 전자소자 개발을 위한 핵심 기술들의 발전은 아직 초기 단계에 있다. 따라서 이 논문을 통해 탄소 나노튜브를 유연 전자소자에 적용시킬 수 있는 새로운 기술을 소개하고자 한다. 첫번째로 탄소 나노튜브와 유연 전자소자의 소자 디자인을 이용하여 피부위에 증착 가능한 비휘발성 메모리 소자를 제작하였고, 해당 기술을 이용하여 피부위에서 안전하게 동작할 수 있는 다양한 기초 회로들을 구현하였다. 탄소 나노튜브 기반 메모리 전자 소자 및 회로는 다양한 외부 응력이 가해져도 안정적으로 동작을 하였고, 개발된 기술을 통해 보다 실용적인 탄소 나노튜브 기반 유연 전자 소자의 제작 조건을 확립할 수 있었다. 두번째로 위에 개발된 기술을 바탕으로, 보다 복잡한 탄소 나노튜브 기반 유연 회로 및 구동전압에 따라 발광색이 변환하는 색변환 소자를 제작하여 해당 소자들이 피부위에 부착되어 잘 작동되도록 구현하였다. 그리고 이 두 가지 웨어러블 전자소자를 통합하여 실시간으로 심전도를 측정하여 탄소 나노튜브 기반 전자소자를 통해 해당 신호를 증폭시키고, 신호의 상태를 색변환 소자로 나타낼 수 있는 심전도 모니터 시스템을 구현하였다. 세번째로 진공 증착이 가능한 유연 절연체를 개발하여, 기존의 유연 전자소자들이 가지고 있던 극명한 한계를 극복하였다 (높은 구동 전압, 낮은 집적도, 대면적 소자 선능 균일도 등). 기존의 액상 기반 증착을 위주로 한 유연 전자 소자들은 무기물질 기반 전자소자 대비 극심한 성능 저하를 보여주었는데, 이를 해결하기 위해 새로운 절연물질을 개발하고 탄소 나노튜브 기반 유연 전자소자에 적용하여 그 가능성을 보여주었다.Chapter 1. Introduction 1 1.1 Discovery of CNTs and their benefits for soft electronic applications 1 1.2 Electrical sorting of CNTs 5 1.3 Deposition methods of solution-processed semiconducting CNTs 7 1.4 Conclusion 23 1.5 References 24 Chapter 2. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 32 2.1 Introduction 32 2.2 Experimental section 34 2.3 Results and discussion 36 2.4 Conclusion 62 2.5 References 63 Chapter 3. Wearable Electrocardiogram Monitor Using Carbon Nanotube Electronics and Color-Tunable Organic Light-Emitting Diodes 67 3.1 Introduction 67 3.2 Experimental section 70 3.3 Results and discussion 73 3.4 Conclusion 97 3.5 References 98 Chapter 4. Medium-Scale Electronic Skin Based on Carbon Nanotube Transistors with Vacuum-Deposited Stretchable Dielectric Film 102 4.1 Introduction 102 4.2 Experimental section 106 4.3 Result and discussion 111 4.4 Conclusion 135 4.5 References 136Docto