Study of Radiation Effects on 28nm UTBB FDSOI Technology

With the evolution of modern Complementary Metal-Oxide-Semiconductor (CMOS) technology, transistor feature size has been scaled down to nanometers. The scaling has resulted in tremendous advantages to the integrated circuits (ICs), such as higher speed, smaller circuit size, and lower operating voltage. However, it also creates some reliability concerns. In particular, small device dimensions and low operating voltages have caused nanoscale ICs to become highly sensitive to operational disturbances, such as signal coupling, supply and substrate noise, and single event effects (SEEs) caused by ionizing particles, like cosmic neutrons and alpha particles. SEEs found in ICs can introduce transient pulses in circuit nodes or data upsets in storage cells. In well-designed ICs, SEEs appear to be the most troublesome in a space environment or at high altitudes in terrestrial environment. Techniques from the manufacturing process level up to the system design level have been developed to mitigate radiation effects. Among them, silicon-on-insulator (SOI) technologies have proven to be an effective approach to reduce single-event effects in ICs. So far, 28nm ultra-thin body and buried oxide (UTBB) Fully Depleted SOI (FDSOI) by STMicroelectronics is one of the most advanced SOI technologies in commercial applications. Its resilience to radiation effects has not been fully explored and it is of prevalent interest in the radiation effects community. Therefore, two test chips, namely ST1 and AR0, were designed and tested to study SEEs in logic circuits fabricated with this technology. The ST1 test chip was designed to evaluate SET pulse widths in logic gates. Three kinds of the on-chip pulse-width measurement detectors, namely the Vernier detector, the Pulse Capture detector and the Pulse Filter detector, were implemented in the ST1 chip. Moreover, a Circuit for Radiation Effects Self-Test (CREST) chain with combinational logic was designed to study both SET and SEU effects. The ST1 chip was tested using a heavy ion irradiation beam source in Radiation Effects Facility (RADEF), Finland. The experiment results showed that the cross-section of the 28nm UTBB-FDSOI technology is two orders lower than its bulk competitors. Laser tests were also applied to this chip to research the pulse distortion effects and the relationship between SET, SEU and the clock frequency. Total Ionizing Dose experiments were carried out at the University of Saskatchewan and European Space Agency with Co-60 gammacell radiation sources. The test results showed the devices implemented in the 28nm UTBB-FDSOI technology can maintain its functionality up to 1 Mrad(Si). In the AR0 chip, we designed five ARM Cortex-M0 cores with different logic protection levels to investigate the performance of approximate logic protecting methods. There are three custom-designed SRAM blocks in the test chip, which can also be used to measure the SEU rate. From the simulation result, we concluded that the approximate logic methodology can protect the digital logic efficiently. This research comprehensively evaluates the radiation effects in the 28nm UTBB-FDSOI technology, which provides the baseline for later radiation-hardened system designs in this technology

Study of Radiation-Tolerant SRAM Design

Static Random Access Memories (SRAMs) are important storage components and widely used in digital systems. Meanwhile, with the continuous development and progress of aerospace technologies, SRAMs are increasingly used in electronic systems for spacecraft and satellites. Energetic particles in space environments can cause single event upsets normally referred as soft errors in the memories, which can lead to the failure of systems. Nowadays electronics at the ground level also experience this kind of upset mainly due to cosmic neutrons and alpha particles from packaging materials, and the failure rate can be 10 to 100 times higher than the errors from hardware failures. Therefore, it is important to study the single event effects in SRAMs and develop cost-effective techniques to mitigate these errors. The objectives of this thesis are to evaluate the current mitigation techniques of single event effects in SRAMs and develop a radiation-tolerant SRAM based on the developed techniques. Various radiation sources and the mechanism of their respective effects in Complementary Metal-Oxide Semiconductors(CMOS) devices are reviewed first in the thesis. The radiation effects in the SRAMs, specifically single event effects are studied, and various mitigation techniques are evaluated. Error-correcting codes (ECC) are studied in the thesis since they can detect and correct single bit errors in the cell array, and it is a effective method with low overhead in terms of area, speed, and power. Hamming codes are selected and implemented in the design of the SRAM, to protect the cells from single event upsets in the SRAM. The simulation results show they can prevent the single bit errors in the cell arrays with low area and speed overhead. Another important and vulnerable part of SRAMs in radiation environments is the sense amplifier. It may not generate the correct output during the reading operation if it is hit by an energetic particle. A novel fault-tolerant sense amplifier is introduced and validated with simulations. The results showed that the performance of the new design can be more than ten times better than that of the reference design. When combining the SRAM cell arrays protected with ECC and the radiation-tolerant hardened sense amplifiers, the SRAM can achieve high reliability with low speed and area overhead

Study of Radiation Tolerant Storage Cells for Digital Systems

Single event upsets (SEUs) are a significant reliability issue in semiconductor devices. Fully Depleted Silicon-on-Insulator (FDSOI) technologies have been shown to exhibit better SEU performance compared to bulk technologies. This is attributed to the thin Silicon (Si) layer on top of a Buried Oxide (BOX) layer, which allows each transistor to function as an insulated Si island, thus reducing the threat of charge-sharing. Moreover, the small volume of the Si in FDSOI devices results in a reduction of the amount of charge induced by an ion strike. The effects of Total Ionizing Dose (TID) on integrated circuits (ICs) can lead to changes in gate propagation delays, leakage currents, and device functionality. When IC circuits are exposed to ionizing radiation, positive charges accumulate in the gate oxide and field oxide layers, which results in reduced gate control and increased leakage current. TID effects in bulk technologies are usually simpler due to the presence of only one gate oxide layer, but FDSOI technologies have a more complex response to TID effects because of the additional BOX layer. In this research, we aim to address the challenges of developing cost-effective electronics for space applications by bridging the gap between expensive space-qualified components and high-performance commercial technologies. Key research questions involve exploring various radiation-hardening-by-design (RHBD) techniques and their trade-offs, as well as investigating the feasibility of radiation-hardened microcontrollers. The effectiveness of RHBD techniques in mitigating soft errors is well-established. In our study, a test chip was designed using the 22-nm FDSOI process, incorporating multiple RHBD Flip-Flop (FF) chains alongside a conventional FF chain. Three distinct types of ring oscillators (ROs) and a 256 kbit SRAM was also fabricated in the test chip. To evaluate the SEU and TID performance of these designs, we conducted multiple irradiation experiments with alpha particles, heavy ions, and gamma-rays. Alpha particle irradiation tests were carried out at the University of Saskatchewan using an Americium-241 alpha source. Heavy ion experiments were performed at the Texas A&M University Cyclotron Institute, utilizing Ne, Ar, Cu, and Ag in a 15 MeV/amu cocktail. Lastly, TID experiments were conducted using a Gammacell 220 Co-60 chamber at the University of Saskatchewan. By evaluating the performance of these designs under various irradiation conditions, we strive to advance the development of cost-effective, high-performance electronics suitable for space applications, ultimately demonstrating the significance of this project. When exposed to heavy ions, radiation-hardened FFs demonstrated varying levels of improvement in SEU performance, albeit with added power and timing penalties compared to conventional designs. Stacked-transistor DFF designs showed significant enhancement, while charge-cancelling and interleaving techniques further reduced upsets. Guard-gate (GG) based FF designs provided additional SEU protection, with the DFR-FF and GG-DICE FF designs showing zero upsets under all test conditions. Schmitt-trigger-based DFF designs exhibited improved SEU performance, making them attractive choices for hardening applications. The 22-nm FDSOI process proved more resilient to TID effects than the 28-nm process; however, TID effects remained prominent, with increased leakage current and SRAM block degradation at high doses. These findings offer valuable insights for designers aiming to meet performance and SER specifications for circuits in radiation environments, emphasizing the need for additional attention during the design phase for complex radiation-hardened circuits

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Alterungsanalyse komplexer analoger integrierter Schaltungen aus Systemsicht

The design of analog circuits ranges from the specifications on system level, the selection of a suitable circuit topology up to the choice of the concrete physical dimensions of components like transistors. The individual steps are performed within computer-aided design environments. These environments are based on a database made available by the semiconductor manufacturers containing process parameters and influences on the components. In particular, the influences to be considered in the design have increased in recent years due to the continuous reduction of the producible structural sizes. Thus, it must be possible to analyze the deviations due to process, temperature, time degradation and, for special applications, radiation influences during the design phase. Conventional approaches regard these additional effects as standing next to the actual design process. As a result, the latter is no longer consistent and it is much more complex to consider different circuits and effects on different abstraction levels within the design flow. The focus of this work lies on the development of a consistent consideration of process, voltage, temperature, aging and radiation influences (PVTAR) during the entire design process of analog circuits to the initial measurement of manufactured circuits. To achieve this goal, a transistor model was extended by the influences to be considered. Thereby, the analysis of the additional effects is seamlessly integrated into conventional design processes and methods. In addition, the possibility of a structured analog design is evaluated. This approach allows the estimation of PVTAR influences on dedicated analog function blocks and their propagation on circuit level. Thus, the enormous simulation effort associated with aging analyses can be reduced. The design and manufacture of circuits is always followed by the measurement of the core properties of these circuits. In the context of this work a method was developed which makes it possible to use all insights from the design of a circuit for the improvement of the measuring results. In addition, the internal parameter sets of individual components can be inferred from the terminal behavior of circuits and systems. Finally, the results of the measurement method can be used for the automated calculation of circuit reliability parameters

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

Ferroelectric transistors (FeFETs) based on doped hafnium oxide (HfO2) have received much attention due to their technological potential in terms of scalability, highspeed, and low-power operation. Unfortunately, however, HfO2-FeFETs also suffer from persistent reliability challenges, specifically affecting retention, endurance, and variability. A deep understanding of the reliability physics of HfO2-FeFETs is an essential prerequisite for the successful commercialization of this promising technology. In this article, we review the literature about the relevant reliability aspects of HfO2-FeFETs. We initially focus on the reliability physics of ferroelectric capacitors, as a prelude to a comprehensive analysis of FeFET reliability. Then, we interpret key reliability metrics of the FeFET at the device level (i.e., retention, endurance, and variability) based on the physical mechanisms previously identified. Finally, we discuss the implications of device-level reliability metrics at both the circuit and system levels. Our integrative approach connects apparently unrelated reliability issues and suggests mitigation strategies at the device, circuit, or system level. We conclude this article by proposing a set of research opportunities to guide future development in this field

Modelling and simulation study of NMOS Si nanowire transistors

Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation. At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture. To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability. Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs

Caractérisation électrique et modélisation du transport dans matériaux et dispositifs SOI avancés

This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres

Techniques d'abstraction pour l'analyse et la mitigation des effets dus à la radiation

The main objective of this thesis is to develop techniques that can beused to analyze and mitigate the effects of radiation-induced soft errors in industrialscale integrated circuits. To achieve this goal, several methods have been developedbased on analyzing the design at higher levels of abstraction. These techniquesaddress both sequential and combinatorial SER.Fault-injection simulations remain the primary method for analyzing the effectsof soft errors. In this thesis, techniques which significantly speed-up fault-injectionsimulations are presented. Soft errors in flip-flops are typically mitigated by selectivelyreplacing the most critical flip-flops with hardened implementations. Selectingan optimal set to harden is a compute intensive problem and the second contributionconsists of a clustering technique which significantly reduces the number offault-injections required to perform selective mitigation.In terrestrial applications, the effect of soft errors in combinatorial logic hasbeen fairly small. It is known that this effect is growing, yet there exist few techniqueswhich can quickly estimate the extent of combinatorial SER for an entireintegrated circuit. The third contribution of this thesis is a hierarchical approachto combinatorial soft error analysis.Systems-on-chip are often developed by re-using design-blocks that come frommultiple sources. In this context, there is a need to develop and exchange reliabilitymodels. The final contribution of this thesis consists of an application specificmodeling language called RIIF (Reliability Information Interchange Format). Thislanguage is able to model how faults at the gate-level propagate up to the block andchip-level. Work is underway to standardize the RIIF modeling language as well asto extend it beyond modeling of radiation-induced failures.In addition to the main axis of research, some tangential topics were studied incollaboration with other teams. One of these consisted in the development of a novelapproach for protecting ternary content addressable memories (TCAMs), a specialtype of memory important in networking applications. The second supplementalproject resulted in an algorithm for quickly generating approximate redundant logicwhich can protect combinatorial networks against permanent faults. Finally anapproach for reducing the detection time for errors in the configuration RAM forField-Programmable Gate-Arrays (FPGAs) was outlined.Les effets dus à la radiation peuvent provoquer des pannes dans des circuits intégrés. Lorsqu'une particule subatomique, fait se déposer une charge dans les régions sensibles d'un transistor cela provoque une impulsion de courant. Cette impulsion peut alors engendrer l'inversion d'un bit ou se propager dans un réseau de logique combinatoire avant d'être échantillonnée par une bascule en aval.Selon l'état du circuit au moment de la frappe de la particule et selon l'application, cela provoquera une panne observable ou non. Parmi les événements induits par la radiation, seule une petite portion génère des pannes. Il est donc essentiel de déterminer cette fraction afin de prédire la fiabilité du système. En effet, les raisons pour lesquelles une perturbation pourrait être masquée sont multiples, et il est de plus parfois difficile de préciser ce qui constitue une erreur. A cela s'ajoute le fait que les circuits intégrés comportent des milliards de transistors. Comme souvent dans le contexte de la conception assisté par ordinateur, les approches hiérarchiques et les techniques d'abstraction permettent de trouver des solutions.Cette thèse propose donc plusieurs nouvelles techniques pour analyser les effets dus à la radiation. La première technique permet d'accélérer des simulations d'injections de fautes en détectant lorsqu'une faute a été supprimée du système, permettant ainsi d'arrêter la simulation. La deuxième technique permet de regrouper en ensembles les éléments d'un circuit ayant une fonction similaire. Ensuite, une analyse au niveau des ensemble peut être faite, identifiant ainsi ceux qui sont les plus critiques et qui nécessitent donc d'être durcis. Le temps de calcul est ainsi grandement réduit.La troisième technique permet d'analyser les effets des fautes transitoires dans les circuits combinatoires. Il est en effet possible de calculer à l'avance la sensibilité à des fautes transitoires de cellules ainsi que les effets de masquage dans des blocs fréquemment utilisés. Ces modèles peuvent alors être combinés afin d'analyser la sensibilité de grands circuits. La contribution finale de cette thèse consiste en la définition d'un nouveau langage de modélisation appelé RIIF (Reliability Information Ineterchange Format). Ce langage permet de décrire le taux des fautes dans des composants simples en fonction de leur environnement de fonctionnement. Ces composants simples peuvent ensuite être combinés permettant ainsi de modéliser la propagation de leur fautes vers des pannes au niveau système. En outre, l'utilisation d'un langage standard facilite l'échange de données de fiabilité entre les partenaires industriels.Au-delà des contributions principales, cette thèse aborde aussi des techniques permettant de protéger des mémoires associatives ternaires (TCAMs). Les approches classiques de protection (codes correcteurs) ne s'appliquent pas directement. Une des nouvelles techniques proposées consiste à utiliser une structure de données qui peut détecter, d'une manière statistique, quand le résultat n'est pas correct. La probabilité de détection peut être contrôlée par le nombre de bits alloués à cette structure. Une autre technique consiste à utiliser un détecteur de courant embarqué (BICS) afin de diriger un processus de fond directement vers le région touchée par une erreur. La contribution finale consiste en un algorithme qui permet de synthétiser de la logique combinatoire afin de protéger des circuits combinatoires contre les fautes transitoires.Dans leur ensemble, ces techniques facilitent l'analyse des erreurs provoquées par les effets dus à la radiation dans les circuits intégrés, en particulier pour les très grands circuits composés de blocs provenant de divers fournisseurs. Des techniques pour mieux sélectionner les bascules/flip-flops à durcir et des approches pour protéger des TCAMs ont étés étudiées