Modeling the Impact of Process Variation on Resistive Bridge Defects

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V) and effective mobility (ueff) where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE

Variation aware analysis of bridging fault testing

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drive strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality

Investigation into voltage and process variation-aware manufacturing test

Increasing integration and complexity in IC design provides challenges for manufacturing testing. This thesis studies how process and supply voltage variation influence defect behaviour to determine the impact on manufacturing test cost and quality. The focus is on logic testing of static CMOS designs with respect to two important defect types in deep submicron CMOS: resistive bridges and full opens. The first part of the thesis addresses testing for resistive bridge defects in designs with multiple supply voltage settings. To enable analysis, a fault simulator is developed using a supply voltage-aware model for bridge defect behaviour. The analysis shows that for high defect coverage it is necessary to perform test for more than one supply voltage setting, due to supply voltage-dependent behaviour. A low-cost and effective test method is presented consisting of multi-voltage test generation that achieves high defect coverage and test set size reduction without compromise to defect coverage. Experiments on synthesised benchmarks with realistic bridge locations validate the proposed method.The second part focuses on the behaviour of full open defects under supply voltage variation. The aim is to determine the appropriate value of supply voltage to use when testing. Two models are considered for the behaviour of full open defects with and without gate tunnelling leakage influence. Analysis of the supply voltage-dependent behaviour of full open defects is performed to determine if it is required to test using more than one supply voltage to detect all full open defects. Experiments on synthesised benchmarks using an extended version of the fault simulator tool mentioned above, measure the quantitative impact of supply voltage variation on defect coverage.The final part studies the impact of process variation on the behaviour of bridge defects. Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation

As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide.Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens.The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy

Mammalian Sperm Motility: Observation and Theory

Mammalian spermatozoa motility is a subject of growing importance because of rising human infertility and the possibility of improving animal breeding. We highlight opportunities for fluid and continuum dynamics to provide novel insights concerning the mechanics of these specialized cells, especially during their remarkable journey to the egg. The biological structure of the motile sperm appendage, the flagellum, is described and placed in the context of the mechanics underlying the migration of mammalian sperm through the numerous environments of the female reproductive tract. This process demands certain specific changes to flagellar movement and motility for which further mechanical insight would be valuable, although this requires improved modeling capabilities, particularly to increase our understanding of sperm progression in vivo. We summarize current theoretical studies, highlighting the synergistic combination of imaging and theory in exploring sperm motility, and discuss the challenges for future observational and theoretical studies in understanding the underlying mechanics.\ud Acronyms and Definitions\ud Acrosome: the cap of the sperm head containing enzymes allowing penetration of the zona pellucida via the acrosome reaction\ud Adenosine triphosphate (ATP): the currency unit of chemical energy transfer in living cells\ud Axoneme: a phylogenetically conserved structure within the eukaryotic flagellum consisting of a ring of nine microtubule doublets and a central pair, frequently referred to as 9 + 2\ud Bending moment density: the moment per unit length associated with flagellar bending; it can be divided into a hydrodynamic moment, an elastic moment (from the flagellar bending stiffness), an active moment (generated by dyneins exerting forces between adjacent microtubule doublets), and a passive moment resisting shear\ud Capacitation: the physiological state of a sperm required for fertilization, which is accompanied by the motility patterns associated with hyperactivation, characterized in saline by high-amplitude asymmetric beating\ud Central pair: a pair of microtubules along the length of the axoneme, symmetrically and slightly offset from the axoneme centerline\ud Cumulus oophorus: the outer vestment of the mammalian egg consisting of hundreds of cells radiating out from the egg embedded within a non-Newtonian hyaluronic acid gel\ud Dynein: a molecular motor within the axoneme, attached between adjacent microtubule doublets, that exerts a shearing force to induce axonemal bending\ud Flagellum: a motile cellular appendage that drives the swimming of sperm and other cells; this article focuses on the eukaryotic flagellum\ud Microtubule doublet: a pair of proteinaceous filament structures running the length of the axoneme; dyneins drive their bending, which induces flagellar motion\ud Mid-piece: the region of a sperm flagellum with a mitochondrial sheath, where ATP is generated\ud Oocyte: the egg\ud Outer dense fibers and fibrous sheath: accessory structures reinforcing the mammalian sperm flagellum; the combined axoneme and accessory structures are referred to as 9+9+2\ud Resistive-force theory: an approximation for the local drag of a slender filament element in Stokes flow (or a viscoelastic generalization thereof)\ud Rheotaxis: directed motility in response to the influence of fluid flow\ud Shear: in the context of the flagellum, the relative movement of adjacent microtubule doublets\ud Slender-body theory: an improved approximation for the local drag on a slender filament element in Stokes flow (or a viscoelastic generalization thereof)\ud Zona pellucida: a tough glycoprotein coat between the human egg and the cumulus oophorus, which a sperm must penetrate for successful fertilizatio

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs

Manufacturing defects that do not affect the functional operation of low power Integrated Circuits (ICs) can nevertheless impact their power saving capability. We show that stuck-ON faults on the power switches and resistive bridges between the power networks can impair the power saving capability of power-gating designs. For quantifying the impact of such faults on the power savings of power-gating designs, we propose a diagnosis technique that targets bridges between the power networks. The proposed technique is based on the static power analysis of a power-gating design in stand-by mode and it utilizes a novel on-chip signature generation unit, which is sensitive to the voltage level between power rails, the measurements of which are processed off-line for the diagnosis of bridges that can adversely affect power savings. We explore, through SPICE simulation of the largest IWLS’05 benchmarks synthesised using a 32 nm CMOS technology, the trade-offs achieved by the proposed technique between diagnosis accuracy and area cost and we evaluate its robustness against process variation. The proposed technique achieves a diagnosis resolution that is higher than 98.6% and 97.9% for bridges of R ≳ 10MΩ(weak bridges) and bridges of R ≲ 10MΩ (strong bridges), respectively, and a diagnosis accuracy higher than 94.5% for all the examined defects. The area overhead is small and scalable: it is found to be 1.8% and 0.3% for designs with 27K and 157K gate equivalents, respectively

Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology

Kinetic energy harvesting

This paper reviews kinetic energy harvesting as a potential localised power supply for wireless applications. Harvesting devices are typically implemented as resonant devices of which the power output depends upon the size of the inertial mass, the frequency and amplitude of the driving vibrations, the maximum available mass displacement and the damping. Three transduction mechanisms are currently primarily employed to convert mechanical into electrical energy: electromagnetic, piezoelectric and electrostatic. Piezoelectric and electrostatic mechanisms are best suited to small size MEMS implementations, but the power output from such devices is at present limited to a few microwatts. An electromagnetic generator implemented with discrete components has produced a power 120 ?W with the highest recorded efficiency to date of 51% for a device of this size reported to date. The packaged device is 0.8 cm3 and weighs 1.6 grams. The suitability of the technology in space applications will be determined by the nature of the available kinetic energy and the required level of output power. A radioactively coupled device may present an opportunity where suitable vibrations do not exist

Gravito-thermo-electrodynamic extraction of energy from Kerr black holes

The ``force-free" magnetosphere of a Kerr black-hole in the axisymmetric steady-state possesses two integral functions of the stream-function $\Psi$; the field-line angular-velocity (FLAV) $\Omega_{\rm F} (\Psi)$, and the current-function $I(\Psi)$. For the zero-angular-momentum-observer's FLAV, i.e., $\Omega_{F {\omega}}\equiv\Omega_{\rm F}-\omega$, the iso-rotation law breaks down; $\Omega_{\rm F {\omega}}$ vanishes at the null-surface $\cal{S}_{\rm N}$ with $\omega=\Omega_{\rm F}$, where $\omega$ is the frame-dragging angular-velocity, and this gives rise to a subsequent breakdown of the force-free and freezing-in conditions at $\cal{S}_{\rm N}$, and the particle-velocity and the electric-current must vanish at $\cal{S}_{\rm N}$. These impose strong constraints on a possible gap to be constructed at $\cal{S}_{\rm N}$ between the force-free domains, $\cal{D}_{\rm out}$ and $\cal{D}_{\rm in}$. Current circuits, $\cal{C}_{\rm out}$ and $\cal{C}_{\rm in}$, must be closed in each domain, with EMFs $\cal{E}_{\rm out}$ and $\cal{E}_{\rm in}$, respectively, oppositely directed at the inductive membrane $\cal{S}_{\rm N}$ and with resistances $I_{\rm (out)}$ and $I_{\rm (in)}$ at the resistive membranes $\cal{S}_{{\rm ff}\infty}$ and $\cal{S}_{{\rm ffH}}$. The particles pair-produced in $\cal{G}_{\rm N}$ must be ``zero-angular-momentum-particles", which will be dense enough to pin down the poloidal field-lines ${\bf B}_p$ threading $\cal{G}_{\rm N}$, to ensure magnetisation of $\cal{G}_{\rm N}$. The zero-angular-momentum-state of $\cal{G}_{\rm N}$ makes it possible in $\cal{D}_{\rm in}$ that the outgoing-flux $I_{\rm (in)}$ of {\em positive}-angular-momentum from the hole is equivalent to the ingoing-flux $I^{\rm (in)}$ of {\em negative}-angular-momentum from $\cal{G}_{\rm N}$, i.e., $I_{\rm (in)}(\Psi)=-I^{\rm (in)}(\Psi)$. A twin-pulsar model is proposed