Monolithic integration of 1.55 micron photodetectors with GaAs electronics for high speed optical communications

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 1998.Includes bibliographical references (p. 178-194).Integrated optoelectronics has shown exciting promise for high speed optical communication systems. For better system performance and lower cost, monolithic optoelectronic integrated circuits (OEICs) are highly desirable. A novel optoelectronic integration technology for high performance OEICs was proposed and partially developed and termed Aligned Pillar Bonding (APB) process. The work began with applying GaAs-based Epitaxy-on-Electronics (EoE) technology to integrate matched pairs of 1.55 micron InGaAs photodetectors with high speed GaAs electronics, which requires the direct growth of InGaAs on lattice-mismatched GaAs substrates using molecular beam epitaxy (MBE). A customized OEIC chip was designed and fabricated. Lattice-mismatched MBE growth was studied and InGaAs photodetectors on GaAs were produced using the relaxed buffer growth. However, the device performance and uniformity deteriorated significantly from those on lattice-matched InP substrates, and thus unsuitable for high speed OEICs. Aligned pillar bonding (APB) process was hence proposed. APB integrates lattice mismatched materials using aligned, selective area wafer bonding at reduced temperature. The photonic device structures are grown on their lattice matched substrates under optimal growth condition. These structures are patterned into pillars, aligned and bonded into the designated wells on the electronic chips. Subsequent substrate removal and device fabrication results in high density OEICs. 1.55 micron InGaAs photodetectors on GaAs were demonstrated using reduced temperature Pd-assisted wafer bonding, resulting in superior device performance. While the conventional dry etching techniques are impractical to pattern the desired deep pillars, electron cyclotron resonance (ECR) enhanced reactive ion etching (RIE) of InP using chlorine/helium chemistry has been developed, resulting in fast, deep, smooth, and highly anisotropic etching at room temperature. The etching characteristics have been calibrated for both InP and GaAs. Fast etching of InGaP, InAlAs, AlAs, and GaP has also been demonstrated. The etched pillars were subsequently bonded onto a OEIC chip, and initial study of small area pillar to well bonding was performed. APB allows independent optimization of both photonics and electronics for OEIC integration, inherits the wealth of the existing electronics industry, maintains good planarization and high density, permits low parasitics and high performance, and is naturally compatible with large scale manufacturing.by Hao Wang.Ph.D

A novel monolithic focal plane array for mid-IR imaging

The use of Mid-infrared (mid-IR) imagers has great potential for a number of applications in gas sensing and medical diagnostics, but so far for many of those non-defence fields it has been significantly limited by their high price tag. One of the reasons behind the great cost of mid-IR imagers is that most of them need to operate at cryogenic temperatures. Thanks to more than half a century of research, state-of-the-art mid-IR photodetectors have finally achieved premium detection performance without the need for cryogenic cooling. Some of them have even demonstrated very promising results, suggesting room temperature operation is on the horizon. As a result, the cost associated with cooling equipment has been significantly suppressed. However, most mid-IR imagers are still based on hybrid technologies needing a great number of die-level process steps and being prone to connection failure during thermal cycles. The high manufacturing cost this entails is also preventing a wider diffusion of mid-IR imagers. Currently, there is still a lack of an effective monolithic approach able to achieve low-cost mass production of mid-IR imagers in the same way as monolithic integration has been widely used for imagers working at visible wavelengths. This thesis presents a novel monolithic approach for making mid-IR imagers based on co-integration of mid-IR photodetectors with GaAs-based MESFETs on the same chip. The initial focus of the project was the development of the fabrication steps for delivery of prototype devices. In order to achieve monolithic fabrication of pixel devices made in either indium antimonide (InSb) or indium arsenide antimonide (InAsSb) on a gallium arsenide (GaAs) substrate, various highly controllable etch processes, both wet and dry etch based, were established for distinct material layers. Moreover, low temperature annealed Ohmic contacts to both antimonide-based materials and GaAs were used. The processing temperatures used never exceeded 180˚C, preventing degradation of photodetector performance after fabrication of transistors, thus avoiding well-known thermal issues of InSb fabrication. Furthermore, an intermediate step based on polyimide was developed to provide a smoothing section between the lower MESFET and upper photodetector regions of the pixel device. The polyimide planarisation enabled metal interconnects between the fabricated devices regardless of the considerable etch step (> 6 µm) created after multiple mesa etches. Detailed electrical and optical measurements demonstrated that the devices were sensitive to mid-IR radiation in the 3 to 5 µm range at room temperature, and that each pixel could be isolated from its contacts by switching off the co-integrated MESFET. Following the newly developed fabrication flow, InSb-based mid-IR imaging arrays (in two sizes, 4×4 and 8×8) are presented here for the first time, with pixel addressing achieved by monolithically integrated GaAs MESFETs. By demonstrating real-time imaging results obtained from these array devices at room temperature, implementation of a new type of monolithic focal plane array for mid-IR imaging has been confirmed. The device is suitable for further scaling (up to 64×64 pixel and beyond) and potential commercialisation. More importantly, the monolithic approach developed in this work is very flexible, as a number of III-V materials with mid-IR detecting capabilities can be grown on GaAs substrates, meaning alternative semiconductor layer structures could also be investigated in the near future

Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Monolithic integration of etched facet lasers with GaAs VLSI cirucits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (p. 171-177).by Yakov Royter.Ph.D

High performance photodetectors for multimode optical data links

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 233-240).The majority of photodetectors presented in the literature, or available commercially, have dimensions on the order of 50 Ym or smaller, suitable for glass multimode or single mode fibre applications. The recent successful commercialisation of very large core diameter plastic optical fibre in systems based around 650 nm emitters, as well as the recent emergence of new polymer materials enabling relatively low loss at the more standard 780 nm and 850 nm wavelengths, has exposed the need for integrated photodetectors with dimensions well above 100 /m and capable of bitrates from 250 Mb/s for low-cost consumer applications to multiple Gb/s for high performance short reach interconnects. This size-performance regime has been largely ignored until now. This work examines interdigitated detector structures in multiple material systems by measurement and simulation. An optoelectronic frequency response measurement system was designed and implemented for this work, allowing measurement up to 8 GHz using 850 nm or 1550 nm sources. The full expression for frequency response of diffusion current under different illumination scenarios was derived, a topic normally omitted in the discussion of photodetectors, and applied to the analysis of device measurements.(cont.) Silicon detectors of various geometries were fabricated, with measured bandwidths at 5 V reverse bias up to 2 GHz for 200 ym diameter devices and 4 GHz for 50 and 100 ym diameter devices. The latter is the highest bandwidth reported for a silicon detector fabricated in a CMOS-compatible process and biased at a practically accessible voltage. Device performance was confirmed by simulation, and a novel structure is proposed featuring a buried junction on SOI determined by simulation to have twice as high a responsivity-bandwidth product as the best reported devices fabricated on high resistivity SOI. The silicon device structure was modified for epitaxial germanium wafers, and devices were fabricated. The germanium devices were simulated to determine the appropriate technology scaling direction and maximum device dimensions for desired performance specifications.by Wojciech Piotr Giziewicz.Ph.D

Solid State Technology Branch of NASA Lewis Research Center

A collection of papers written by the members of the Solid State Technology Branch of NASA LeRC from Jun. 1991 - Jun. 1992 is presented. A range of topics relating to superconductivity, Monolithic Microwave Circuits (MMIC's), coplanar waveguides, and material characterization is covered