199 research outputs found
Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER
Search based software engineering: Trends, techniques and applications
© ACM, 2012. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version is available from the link below.In the past five years there has been a dramatic increase in work on Search-Based Software Engineering (SBSE), an approach to Software Engineering (SE) in which Search-Based Optimization (SBO) algorithms are used to address problems in SE. SBSE has been applied to problems throughout the SE lifecycle, from requirements and project planning to maintenance and reengineering. The approach is attractive because it offers a suite of adaptive automated and semiautomated solutions in situations typified by large complex problem spaces with multiple competing and conflicting objectives.
This article provides a review and classification of literature on SBSE. The work identifies research trends and relationships between the techniques applied and the applications to which they have been applied and highlights gaps in the literature and avenues for further research.EPSRC and E
A runtime heuristic to selectively replicate tasks for application-specific reliability targets
In this paper we propose a runtime-based selective task replication technique for task-parallel high performance computing applications. Our selective task replication technique is automatic and does not require modification/recompilation of OS, compiler or application code. Our heuristic, we call App_FIT, selects tasks to replicate such that the specified reliability target for an application is achieved. In our experimental evaluation, we show that App FIT selective replication heuristic is low-overhead and highly scalable. In addition, results indicate that complete task replication is overkill for achieving reliability targets. We show that with App FIT, we can tolerate pessimistic exascale error rates with only 53% of the tasks being replicated.This work was supported by FI-DGR 2013 scholarship and the European Community’s
Seventh Framework Programme [FP7/2007-2013] under the Mont-blanc 2
Project (www.montblanc-project.eu), grant agreement no. 610402 and in part by the
European Union (FEDER funds) under contract TIN2015-65316-P.Peer ReviewedPostprint (author's final draft
Internet of things: why we are not there yet
Twenty-one years past since Weiser’s vision of ubiquitous computing (UbiComp) has
been written, and it is yet to be fully fulfilled despite of almost all the needed technologies
already available. Still, the widespread interest in UbiComp and the results in some of its fields
pose a question: why we are not there yet? It seems we miss the ‘octopus’ head. In this paper,
we will try to depict the reasons why we are not there yet, from three different points of view:
interaction media, device integration and applications
Making distributed computing infrastructures interoperable and accessible for e-scientists at the level of computational workflows
As distributed computing infrastructures evolve, and as their take up by user communities is growing, the importance of making different types of infrastructures based on a heterogeneous set of middleware interoperable is becoming crucial. This PhD submission, based on twenty scientific publications, presents a unique solution to the challenge of the seamless interoperation of distributed computing infrastructures at the level of workflows.
The submission investigates workflow level interoperation inside a particular workflow system (intra-workflow interoperation), and also between different workflow solutions (inter-workflow interoperation). In both cases the interoperation of workflow component execution and the feeding of data into these components workflow components are considered.
The invented and developed framework enables the execution of legacy applications and grid jobs and services on multiple grid systems, the feeding of data from heterogeneous file and data storage solutions to these workflow components, and the embedding of non-native workflows to a hosting meta-workflow. Moreover, the solution provides a high level user interface that enables e-scientist end-users to conveniently access the interoperable grid solutions without requiring them to study or understand the technical details of the underlying infrastructure. The candidate has also developed an application porting methodology that enables the systematic porting of applications to interoperable and interconnected grid infrastructures, and facilitates the exploitation of the above technical framework
Mobile Interface for Content-Based Image Management
People make more and more use of digital image acquisition devices to capture screenshots of their everyday life. The growing number of personal pictures raise the problem of their classification. Some of the authors proposed an automatic technique for personal photo album management dealing with multiple aspects (i.e., people, time and background) in a homogenous way. In this paper we discuss a solution that allows mobile users to remotely access such technique by means of their mobile phones, almost from everywhere, in a pervasive fashion. This allows users to classify pictures they store on their devices. The whole solution is presented, with particular regard to the user interface implemented on the mobile phone, along with some experimental results
Designing and modelling selective replication for fault-tolerant HPC applications
Fail-stop errors and Silent Data Corruptions (SDCs) are the most common failure modes for High Performance Computing (HPC) applications. There are studies that address fail-stop errors and studies that address SDCs. However few studies address both types of errors together. In this paper we propose a software-based selective replication technique for HPC applications for both fail-stop errors and SDCs. Since complete replication of applications can be costly in terms of resources, we develop a runtime-based technique for selective replication. Selective replication provides an opportunity to meet HPC reliability targets while decreasing resource costs. Our technique is low-overhead, automatic and completely transparent to the user.This work is supported in part by the European Union Mont-blanc 2 Project (www.montblanc-project.eu), grant
agreement no. 610402 and the FEDER funds under contract TIN2015-65316-P.Peer ReviewedPostprint (author's final draft
Time-Sliced Quantum Circuit Partitioning for Modular Architectures
Current quantum computer designs will not scale. To scale beyond small
prototypes, quantum architectures will likely adopt a modular approach with
clusters of tightly connected quantum bits and sparser connections between
clusters. We exploit this clustering and the statically-known control flow of
quantum programs to create tractable partitioning heuristics which map quantum
circuits to modular physical machines one time slice at a time. Specifically,
we create optimized mappings for each time slice, accounting for the cost to
move data from the previous time slice and using a tunable lookahead scheme to
reduce the cost to move to future time slices. We compare our approach to a
traditional statically-mapped, owner-computes model. Our results show strict
improvement over the static mapping baseline. We reduce the non-local
communication overhead by 89.8\% in the best case and by 60.9\% on average. Our
techniques, unlike many exact solver methods, are computationally tractable.Comment: Appears in CF'20: ACM International Conference on Computing Frontier
Enabling Network Security in HPC Systems Using Heterogeneous CMPs
This chapter explores the possibility of using heterogeneous chip multiprocessors (CMPs) for network and system security. It proposes an integer linear programming (ILP)-based methodology to mathematically analyze and provide heterogeneous CMP architectures and task distributions that can reduce the energy consumption of the system. It compares heterogeneous CMPs with homogeneous counterparts and provides experimental evaluation of using both on network security systems. The details of heterogeneous NoC (network-on-chip)-based CMP architecture are discussed in detail. The chapter also discusses the heterogeneous CMP-based network security processor design and advantages. It summarizes the related work on heterogeneous processors in general and their benefits, and explores the related studies on CMP network security processors. The chapter finally indicates that heterogeneous CMPs reduce the energy consumption dramatically compared to homogeneous CMPs. © 2014 John Wiley & Sons, Inc
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