On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

PAD: A New Interactive Knowledge-Based Analog Design Approach

This paper presents a new Procedural Analog Design tool called PAD. It is a chart-based design environment dedicated to the design of analog circuits aiming to optimize design and quality by finding good tradeoffs. This interactive tool allows step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface enables instantaneous visualization of design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). The present version of PAD covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers (OTAs) and different operational amplifier topologies. The basic analog structures' calculator embedded in PAD uses the complete set of equations of the EKV MOS model, which links the equations for weak and strong inversion in a continuous way [1, 2]. Furthermore, PAD provides a layout generator for matched substructures such as current mirrors, cascode stages and differential pair

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Teollisen Internetin käyttöönotto automaatiolaitteissa

Industrial Internet is a term that is used to describe digitalization of industry. It is a research direction in Finland, where there are already various groups studying it. Despite this, the term Industrial Internet is still relatively vague and there is a lack of concreteness around the topic. The objective of this thesis is to explore the current status of Industrial Internet and study the capabilities of automation devices from an Industrial Internet point of view. I explore Industrial Internet through a literary review where I study various use cases. The use cases of Industrial Internet are divided into two main types: platform centric and machine to machine (M2M) communication centric. The use cases provide a list of characteristics and requirements for Industrial Internet from these two perspectives. General requirements are, for example scalability and flexibility, which are achieved through various IT technologies, such as Service-Oriented-Architecture. This thesis also consists of a practical part where I configured the control logic and data collection for a test bed that simulates drop tests of active magnetic bearings. The control logic consists of a programmable logic controller and corresponding software. The data collection consists of software for collecting and analyzing measurement data and the measuring equipment. After the literary review and practical part, I propose the creation of a cloud based Industrial Internet platform around the active magnetic test bed. The purpose of the platform is to provide a direction for further research. The creation of the platform consists of two phases: first phase includes the creation of the platform so that the test bed achieves current functionality but cloud based. The second phase consists of changing the platform to meet the requirements of the literature review. The end results will be an application independent system solution for Industrial Internet.Teollinen Internet on termi, jolla kuvataan teollisuuden digitalisaatiota. Aihe on kasvavan kiinnostuksen kohde ja esim. Suomessa on useita tahoja, jotka panostavat aiheen tutkimukseen. Siltikin Teollinen Internet on käsitteenä epäselvä ja sitä vaivaa konkretian puute. Tämän työn tarkoituksena on tutustua Teollisen Internetin nykytilaan ja automaatiolaitteiden ominaisuuksiin Teollisen Internetin näkökulmasta. Teollisen Internetin esimerkit jakautuvat pääasiassa kahteen luokkaan: alustalähtöisiin ja koneiden väliseen kommunikaatioon (M2M-kommunikaatio). Esimerkit tarjoavat listan ominaisuuksia ja vaatimuksia Teolliselle Internetille kummastakin näkökulmasta. Yleisiä ominaisuuksia ovat esimerkiksi skaalattavuus ja joustavuus, jotka saavutetaan erilaisilla tietoteknisillä vaatimuksilla, esim. palvelukeskeisellä arkkitehtuurilla. Lisäksi työhön kuuluu käytännön osuus, jossa kirjoitin ohjainlogiikan ja datankeräyksen testilaitteeseen, joka simuloi aktiivimagneettilaakerien pudotuskokeita. Ohjainlogiikka koostui PLC-laitteesta ja siihen liittyvistä ohjelmistoista. Datan keräys koostui mittausdatan keräykseen ja purkamiseen vaadittavista ohjelmistoista sekä laitteistosta. Kirjallisuudesta kerättyjen vaatimusten ja käytännön kokemuksien perusteella esitän pilvipohjaisen, Teolliseen Internetiin suunnatun ohjelmistoalustan kehittämistä testilaitteen ympärille. Ohjelmistoalusta voi toimia yliopistollisen jatkotutkimuksen pohjana. Ohjelmistoalustan toteuttaminen tapahtuu kahdessa vaiheessa: ensimmäisessä vaiheessa kehitetään pilvipohjainen alusta, joka saavuttaa testilaitteiston nykyisen toiminnallisuuden. Toisessa vaiheessa ohjelmistoalusta muutetaan vastaamaan Teollisen Internetin vaatimuksia, jolla saavutetaan sovellusriippumaton järjestelmäratkaisu