2,186 research outputs found
Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis
This paper aims at integrating three powerful techniques namely Deep
Learning, Approximate Computing, and Low Power Design into a strategy to
optimize logic at the synthesis level. We utilize advances in deep learning to
guide an approximate logic synthesis engine to minimize the dynamic power
consumption of a given digital CMOS circuit, subject to a predetermined error
rate at the primary outputs. Our framework, Deep-PowerX, focuses on replacing
or removing gates on a technology-mapped network and uses a Deep Neural Network
(DNN) to predict error rates at primary outputs of the circuit when a specific
part of the netlist is approximated. The primary goal of Deep-PowerX is to
reduce the dynamic power whereas area reduction serves as a secondary
objective. Using the said DNN, Deep-PowerX is able to reduce the exponential
time complexity of standard approximate logic synthesis to linear time.
Experiments are done on numerous open source benchmark circuits. Results show
significant reduction in power and area by up to 1.47 times and 1.43 times
compared to exact solutions and by up to 22% and 27% compared to
state-of-the-art approximate logic synthesis tools while having orders of
magnitudes lower run-time
Model-based dependability analysis : state-of-the-art, challenges and future outlook
Abstract: Over the past two decades, the study of model-based dependability analysis has gathered significant research interest. Different approaches have been developed to automate and address various limitations of classical dependability techniques to contend with the increasing complexity and challenges of modern safety-critical system. Two leading paradigms have emerged, one which constructs predictive system failure models from component failure models compositionally using the topology of the system. The other utilizes design models - typically state automata - to explore system behaviour through fault injection. This paper reviews a number of prominent techniques under these two paradigms, and provides an insight into their working mechanism, applicability, strengths and challenges, as well as recent developments within these fields. We also discuss the emerging trends on integrated approaches and advanced analysis capabilities. Lastly, we outline the future outlook for model-based dependability analysis
Fast and accurate SER estimation for large combinational blocks in early stages of the design
Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt , a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness and Feder Funds under grant TIN2013-44375-R, by the Generalitat de Catalunya under grant FI-DGR 2016, and by the FP7 program of the EU under contract FP7-611404 (CLERECO).Peer ReviewedPostprint (author's final draft
A Fast Pruning Technique for Low-Power Inexact Circuit Design
Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced technology scaling and power density increase, inexact circuits appear to be very promising as a solution. In this paper, we present a novel pruning technique developed as a logic level method to select and prune parts of a digital circuit. The error is computed at each pruning step using probabilistic error propagation and Hamming distance computation, making the evaluation possible at runtime. The technique was validated on several parallel adder architectures. Experimental results proved the efficiency of the technique with Energy-Delay-Area product reduction of 1.8× for less than 10−4% of relative error on the considered benchmarks at 45-nm technology node
ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN
As the MOSFET dimensions scale down towards nanoscale level, the reliability of
circuits based on these devices decreases. Hence, designing reliable systems using
these nano-devices is becoming challenging. Therefore, a mechanism has to be
devised that can make the nanoscale systems perform reliably using unreliable circuit
components. The solution is fault-tolerant circuit design. Markov Random Field
(MRF) is an effective approach that achieves fault-tolerance in integrated circuit
design. The previous research on this technique suffers from limitations at the design,
simulation and implementation levels. As improvements, the MRF fault-tolerance
rules have been validated for a practical circuit example. The simulation framework is
extended from thermal to a combination of thermal and random telegraph signal
(RTS) noise sources to provide a more rigorous noise environment for the simulation
of circuits build on nanoscale technologies. Moreover, an architecture-level
improvement has been proposed in the design of previous MRF gates. The redesigned
MRF is termed as Improved-MRF.
The CMOS, MRF and Improved-MRF designs were simulated under application
of highly noisy inputs. On the basis of simulations conducted for several test circuits,
it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10
times more noise-tolerant than the CMOS alternatives. The number of transistors, on
the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF
respectively (as compared to the CMOS). Therefore, in order to provide a trade-off
between reliability and the area overhead required for obtaining a fault-tolerant
circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this
research work. The value of RAI exceeds around 1.3 and 40 times for MRF and
Improved-MRF respectively as compared to CMOS design which makes Improved-
MRF to be still 30 times more efficient circuit design than MRF in terms of
maintaining a suitable trade-off between reliability and area-consumption of the
circuit
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
Interpolation Methods for Binary and Multivalued Logical Quantum Gate Synthesis
A method for synthesizing quantum gates is presented based on interpolation
methods applied to operators in Hilbert space. Starting from the diagonal forms
of specific generating seed operators with non-degenerate eigenvalue spectrum
one obtains for arity-one a complete family of logical operators corresponding
to all the one-argument logical connectives. Scaling-up to n-arity gates is
obtained by using the Kronecker product and unitary transformations. The
quantum version of the Fourier transform of Boolean functions is presented and
a Reed-Muller decomposition for quantum logical gates is derived. The common
control gates can be easily obtained by considering the logical correspondence
between the control logic operator and the binary propositional logic operator.
A new polynomial and exponential formulation of the Toffoli gate is presented.
The method has parallels to quantum gate-T optimization methods using powers of
multilinear operator polynomials. The method is then applied naturally to
alphabets greater than two for multi-valued logical gates used for quantum
Fourier transform, min-max decision circuits and multivalued adders
Methods and architectures based on modular redundancy for fault-tolerant combinational circuits
Dans cette thèse, nous nous intéressons à la recherche d architectures fiables pour les circuits logiques. Par fiable , nous entendons des architectures permettant le masquage des fautes et les rendant de ce fait tolérantes" à ces fautes. Les solutions pour la tolérance aux fautes sont basées sur la redondance, d où le surcoût qui y est associé. La redondance peut être mise en oeuvre de différentes manières : statique ou dynamique, spatiale ou temporelle. Nous menons cette recherche en essayant de minimiser tant que possible le surcoût matériel engendré par le mécanisme de tolérance aux fautes. Le travail porte principalement sur les solutions de redondance modulaire, mais certaines études développées sont beaucoup plus générales.In this thesis, we mainly take into account the representative technique Triple Module Redundancy (TMR) as the reliability improvement technique. A voter is an necessary element in this kind of fault-tolerant architectures. The importance of reliability in majority voter is due to its application in both conventional fault-tolerant design and novel nanoelectronic systems. The property of a voter is therefore a bottleneck since it directly determines the whole performance of a redundant fault-tolerant digital IP (such as a TMR configuration). Obviously, the efficacy of TMR is to increase the reliability of digital IP. However, TMR sometimes could result in worse reliability than a simplex function module could. A better understanding of functional and signal reliability characteristics of a 3-input majority voter (majority voting in TMR) is studied. We analyze them by utilizing signal probability and boolean difference. It is well known that the acquisition of output signal probabilities is much easier compared with the obtention of output reliability. The results derived in this thesis proclaim the signal probability requirements for inputs of majority voter, and thereby reveal the conditions that TMR technique requires. This study shows the critical importance of error characteristics of majority voter, as used in fault-tolerant designs. As the flawlessness of majority voter in TMR is not true, we also proposed a fault-tolerant and simple 2-level majority voter structure for TMR. This alternative architecture for majority voter is useful in TMR schemes. The proposed solution is robust to single fault and exceeds those previous ones in terms of reliability.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF
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