On scheduling input queued cell switches

Output-queued switching, though is able to offer high throughput, guaranteed delay and fairness, lacks scalability owing to the speed up problem. Input-queued switching, on the other hand, is scalable, and is thus becoming an attractive alternative. This dissertation presents three approaches toward resolving the major problem encountered in input-queued switching that has prohibited the provision of quality of service guarantees. First, we proposed a maximum size matching based algorithm, referred to as min-max fair input queueing (MFIQ), which minimizes the additional delay caused by back pressure, and at the same time provides fair service among competing sessions. Like any maximum size matching algorithm, MFIQ performs well for uniform traffic, in which the destinations of the incoming cells are uniformly distributed over all the outputs, but is not stable for non-uniform traffic. Subse-quently, we proposed two maximum weight matching based algorithms, longest normalized queue first (LNQF) and earliest due date first matching (EDDFM), which are stable for both uniform and non-uniform traffic. LNQF provides fairer service than longest queue first (LQF) and better traffic shaping than oldest cell first (OCF), and EDDEM has lower probability of delay overdue than LQF, LNQF, and OCF. Our third approach, referred to as store-sort-and-forward (SSF), is a frame based scheduling algorithm. SSF is proved to be able to achieve strict sense 100% throughput, and provide bounded delay and delay jitter for input-queued switches if the traffic conforms to the (r, T) model

Everything Matters in Programmable Packet Scheduling

Programmable packet scheduling allows the deployment of scheduling algorithms into existing switches without need for hardware redesign. Scheduling algorithms are programmed by tagging packets with ranks, indicating their desired priority. Programmable schedulers then execute these algorithms by serving packets in the order described in their ranks. The ideal programmable scheduler is a Push-In First-Out (PIFO) queue, which achieves perfect packet sorting by pushing packets into arbitrary positions in the queue, while only draining packets from the head. Unfortunately, implementing PIFO queues in hardware is challenging due to the need to arbitrarily sort packets at line rate based on their ranks. In the last years, various techniques have been proposed, approximating PIFO behaviors using the available resources of existing data planes. While promising, approaches to date only approximate one of the characteristic behaviors of PIFO queues (i.e., its scheduling behavior, or its admission control). We propose PACKS, the first programmable scheduler that fully approximates PIFO queues on all their behaviors. PACKS does so by smartly using a set of strict-priority queues. It uses packet-rank information and queue-occupancy levels at enqueue to decide: whether to admit packets to the scheduler, and how to map admitted packets to the different queues. We fully implement PACKS in P4 and evaluate it on real workloads. We show that PACKS: better-approximates PIFO than state-of-the-art approaches and scales. We also show that PACKS runs at line rate on existing hardware (Intel Tofino).Comment: 12 pages, 12 figures (without references and appendices

Experimental survey of FPGA-based monolithic switches and a novel queue balancer

This paper studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot “hide” multiple iterations of scheduling that are required to achieve a modest scheduling performance.Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources

Dynamic Traffic Scheduling and Resource Reservation Algorithms for Output-Buffered Switches

Scheduling algorithms implemented in Internet switches have been dominated by the best-effort and guaranteed service models. Each of these models encompasses the extreme ends of the correlation spectrum between service guarantees and resource utilisation. Recent advancements in adaptive applications have motivated active research in predictive service models and dynamic resource reservation algorithms. The OCcuPancy_Adjusting (OCP_A) is a scheduling algorithm focused on the design of the above-mentioned research areas. Previously, this algorithm has been analysed for a unified resource reservation and scheduling algorithm while implementing a tail discarding strategy. However, the differentiated services provided by the OCP _A algorithm can be further enhanced. In this dissertation, four new algorithms are proposed. Three are extensions of the OCP _A. The fourth algorithm is an enhanced version of the Virtual Clock (VC) algorithm, denoted as ACcelErated (ACE) scheduler. The first algorithm is a priority scheduling algorithm (i.e. known as the M-Tier algorithm) incorporated with a multitier dynamic resource reservation algorithm. Periodical resource reallocations are implemented. Thus. enabling each tier's resource utilisation to converge to its desired Quality of Service (QoS) operating point. In addition. the algorithm integrates a cross-sharing concept of unused resources between the various hierarchical levels to exemplify the respective QoS sensitivity. In the second algorithm. a control parameter is integrated into the M-Tier algorithm to ensure reduction of delay segregation effects towards packet loss sensitive traffic. The third algorithm, introduces a delay approximation algorithm to justify packet admission. The fourth algorithm enhances the VC scheduling algorithm. This is performed via the incorporation of dynamic features in the computation of the VC scheduling tag. Subsequently, the delay bound limitation of the parameter is eliminated

Project DIANA - Converging and Integrating IP and ATM for real-time applications

The evolution of IP and ATM share some common drivers. Both of them are addressing efficient network resource utilisation. In order to evaluate the options and combinations offered by these technologies the DIANA project is looking into the areas where ATM and IP both overlap and complete each other, that is QoS interworking between ATM and IP. This is achieved by investigating RSVP-over-ATM approach. This solution is compared with two IP level approaches: Differentiated Services and Scalable Resource Reservation Protocol (SRP)