Computer aids for the design of large scale integrated circuits.

The work described in this thesis is concerned with the development of CADIC (Computer Aided Design of Integrated Circuits), a suite of computer programs which allows the user to design integrated circuit layouts at the geometric level. Initially, a review of existing computer aids to integrated circuit design is carried out. Advantages and disadvantages of each computer aid is discused, and the approach taken by CADIC justified in the light of the review. The hardware associated with a design aid can greatly influence its performance and useability. For this reason, a critical review of available graphic terminals is also undertaken. The requirements, logistics, and operation of CADIC is then discussed in detail. CADIC provides a consise range of features to aid in the design and testing of integrated circuit layouts. The most important features are however CADIC's high efficiency in processing layout data, and the implementation of complete on-line design rule checking. Utilization of these features allows CADIC to substantially reduce the lengthy design turnaround time normally associated with manual design aids. Finally, the performance of CADIC is presented. Analysis of the results show that CADIC is very efficient at data processing, especially when small sections of the layout are considered. CADIC can also perform complete on-line design rule checking well within the time it takes the designer to start adding the next shape

Custom Integrated Circuits

Contains reports on three research projects.U.S. Air Force (Contract F49620-81-C-0054)National Science Foundation (Grant ECS81-18160

An Algorithm for Automated Printed Circuit Board Layout and Routing Evaluation

An algorithm has been developed to evaluate printed circuit boards that are designed using automated board layout and routing software. The algorithm analyzes aspects of component placement and trace routing while searching for violations of basic EMC design principles. The algorithm is implemented in code designed to work with a widely used board layout and routing program. This code can help novice and experienced circuit board designers to avoid mistakes that may result in serious electromagnetic compatibility problems

A Framework for the Implementation of an ISO 9000 Based Certification Program for Printed Circuit Board Manufacturers

ISO 9000:2000 is the newest version of the ISO 9000 family of standards. Unlike the 1994 version, it does not distinguish between servicing, testing and designing standards. It emphasizes quality improvement rather than quality control and briefly explains how to implement the Plan-Do-Check- Act (PDCA) cycle for improvement and the use of statistical techniques to improve the quality of process and product instead of controlling the quality of the output. The thesis explains why companies need to be certified and how to implement quality improvement programs. The objective of this thesis is to provide generic certification guidelines for printed circuit board manufacturers, based on ISO 9000:2000 standard. This standardized framework could assist companies in achieving ISO 9000 certification. Since every manufacturer has its own proprietary set of controls on their processes, these generic guidelines provide an opportunity for the user to plug in their own information and to write their own processes. Another objective of this thesis is to introduce a methodology for the implementation of the various methods and tools that can be applied for process improvement in printed circuit boards manufacturing

Implementation of a design rule checker for silicon wafer fabrication

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (leaves 90-92).by Evren R. Ünver.M.Eng

Micro-circuit reticle fabrication: an investigation of a silver halide emulsion as a portable conformable mask

An investigation of the possibility of spin-coating a silver halide emusion similar to that used on Kodak HRP plates onto a positive resist coating reticle blank was made. By changing the cating weight and temperature of the emulsion it was found that the emulsion could be coated onto the reticle without harm to the positive resist material. A five micron width line was imaged successfully and measured in the final chrome sub-layer of the reticle

The Automatic Synthesis of Fault Tolerant and Fault Secure VLSI Systems

This thesis investigates the design of fault tolerant and fault secure (FTFS) systems within the framework of silicon compilation. Automatic design modification is used to introduce FTFS characteristics into a design. A taxonomy of FTFS techniques is introduced and is used to identify a number of features which an "automatic design for FTFS" system should exhibit. A silicon compilation system, Chip Churn 2 (CC2), has been implemented and has been used to demonstrate the feasibility of automatic design of FTFS systems. The CC2 system provides a design language, simulation facilities and a back-end able to produce CMOS VLSI designs. A number of FTFS design methods have been implemented within the CC2 environment; these methods range from triple modular redundancy to concurrent parity code checking. The FTFS design methods can be applied automatically to general designs in order to realise them as FTFS systems. A number of example designs are presented; these are used to illustrate the FTFS modification techniques which have been implemented. Area results for CMOS devices are presented; this allows the modification methods to be compared. A number of problems arising from the methods are highlighted and some solutions suggested