Operating System Concepts for Reconfigurable Computing: Review and Survey

One of the key future challenges for reconfigurable computing is to enable higher design productivity and a more easy way to use reconfigurable computing systems for users that are unfamiliar with the underlying concepts. One way of doing this is to provide standardization and abstraction, usually supported and enforced by an operating system. This article gives historical review and a summary on ideas and key concepts to include reconfigurable computing aspects in operating systems. The article also presents an overview on published and available operating systems targeting the area of reconfigurable computing. The purpose of this article is to identify and summarize common patterns among those systems that can be seen as de facto standard. Furthermore, open problems, not covered by these already available systems, are identified

RTOS Control of Hardware Processes

In this thesis, adding hardware-process support to Microcontroller Real-time Operating System Version 2 (MicroC/OS-II) is proposed. MicroC/OS-II is a hard real-time operating system (RTOS), mostly written in the C programming language. MicroC/OS-II is designed to manage limited resources within embedded systems, and it can only execute and control software processes performed in the same processor system. MicroC/OS-II has been modified in order to manage external hardware processes. These hardware processes are implemented on a Nexys 3 Spartan-6 FPGA Board. In this thesis, MicroC/OS-II is already ported to run on an EVBplus HCS12 development board with CodeWarrior Embedded Software Development Tools from Freescale Semiconductor Inc. Modifications are applied on MicroC/OS-II interrupt system to manage hardware processes, and SPI protocol and parallel interface are set up to communicate between the HCS12 trainer and the FPGA board. The work is illustrated by designing a satellite attitude controller, using variable structure control (VSC)

Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking

With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are required to have excellent hardware programming skills and unique optimization techniques to explore the potential of FPGA resources fully. Intermediate frameworks above hardware circuits are proposed to improve either performance or productivity by leveraging parallel programming models beyond the multi-core era. In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework, which targets enhancing productivity without losing performance. It helps designers develop parallelized applications and implement them on FPGAs. The PolyPC framework implements a custom hardware platform, on which programs written in an OpenCL-like programming model can launch. Additionally, the PolyPC framework extends vendor-provided tools to provide a complete development environment including intermediate software framework, and automatic system builders. Designers\u27 programs can be either synthesized as hardware processing elements (PEs) or compiled to executable files running on software PEs. Benefiting from nontrivial features of re-loadable PEs, and independent group-level schedulers, the multitasking is enabled for both software and hardware PEs to improve the efficiency of utilizing hardware resources. The PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. The results show a maximum 66 times speedup over a dual-core ARM processor and 1043 times speedup over a high-performance MicroBlaze with 125 times of area efficiency. It delivers a significant improvement in response time to high-priority tasks with the priority-aware scheduling. Overheads of multitasking are evaluated to analyze trade-offs. With the help of the design flow, the OpenCL application programs are converted into executables through the front-end source-to-source transformation and back-end synthesis/compilation to run on PEs, and the framework is generated from users\u27 specifications

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail in this article. These algorithms consider most of the technological constraints existing in modern partially reconfigurable FPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition, the algorithms target other important aspects such as communications and synchronization among the different computations that are carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide range of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined

A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.This work has been supported, within the fund for research groups of the Basque university system IT1440-22, by the Department of Education and, within PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects, by the Hazitek program, both of the Basque Government; the latter also by the Ministerio de Ciencia Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the projects IDI-20201264 and IDI-20220543, and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds)

Preemptive Multitasking auf FPGA-Prozessoren

In dieser Arbeit wird die Umsetzung eines multitaskingfähigen Betriebssystems für FPGA-Prozessoren vorgestellt. Mit diesem Betriebssystem ist es möglich, die Resource FPGA-Prozessor durch mehrere unabhängige Anwendungen gleichzeitig zu nutzen. Der wesentliche Teil der Arbeit beschäftigt sich mit der schnellen Zustandsermittlung einer Schaltung auf dem FPGA-Baustein und zugleich mit der schnellen Zustandsrekonstruktion bei erneuter Ausführung der Schaltung auf dem FPGA-Prozessor. Basierend auf diesen grundlegenden Funktionen ist ein Betriebssystem entstanden, das sowohl effektiv als auch flexibel die Verarbeitung mehrerer unabhängiger Anwendungen auf verschiedenen FPGA-Prozessoren ermöglicht. Zur weiteren Steigerung der Leistungsfähigkeit wurde im Rahmen der Arbeit ein spezieller multitaskingunterstützender FPGA-Prozessor erstellt, der durch seinen Aufbau die Prozesswechselzeiten auf ein Minimum reduziert. Durch den neuartigen Aufbau dieses FPGA-Prozessors kann die Ausführung der Anwendungen nach neuen Modellen erfolgen, die durch parallel arbeitende Schritte den FPGA-Prozessor effektiver nutzen

Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems

[EN] Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor instruction stream. These signatures contain the information required to detect control flow errors during program execution by the main processor. This paper proposes an architecture that offers both fault-tolerance and dynamic cache locking combined. This combination is achieved taking advantage of the fact that watchdog processor signatures are inserted along the program code. Then cache locking information is incorporated into these signatures. And also the required circuitry to inform the cache controller whether to lock or not the instructions fetched by the main processor is added into the watchdog processor. With this approach both fault-tolerant and real-time features are supported by the same hardware, therefore saving room on the silicon die or FPGA size. Results from experiments show that in most cases this approach reaches the same performance than previous, hardware-costly proposals.This work was partially funded by the Plan Nacional de I+D, Comision Interministerial de Ciencia y Tecnologia (FEDER-CICYT) under the project HAR2017-85557-P and Agencia Estatal de Investigacion under the project DPI2016-80303-C2-1-P.Martí-Campoy, A.; Rodríguez-Ballester, F. (2019). Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems. IEEE. 259-265. https://doi.org/10.1109/ETFA.2019.8869168S25926