Design of an Efficient Design for Test (DFT) Architecture and it\u27s Verification Using Universal Verification Methodology

The complexity of the circuit design has been significantly increased from 1980’s till date, and until 80’s, due to less complexity and technology node being down to 180nm, the need for Design for Test (DFT) equipment was not as important. The few System on Chips (SoC) were tested using test patterns sent from the external test equipment. As the technology node shrunk further, the devices became faster and the complexity of S0C’s increased as the chip could accommodate more transistors. The SoC’s have become more vulnerable to physical defects. Quality factor became a major issue, which pushed the industry standard of the test coverage very high i.e. between 98% to 100%. To achieve such a high test coverage, testing the SoC’s by external test equipment demands high test time and test cost. Due to this reason, the DFT architectures within the chip have become popular demand in the industry. With the DFT architectures like Memory-Built In Self Test (MBIST) and Logic- Built In Self Test (LBIST), the memories and core logic embedded in the chip will undergo self test at the speed of functional clock and hence saving test time and test cost. Introducing DFT into the chip implies increase in area due to overhead and increase in power consumption due to additional pins. So, the DFT architectures need to be efficient. This project paper discusses about designing an efficient DFT architecture on SoC by integrating MBIST and LBIST with Joint Test Action Group-Test Access Port (JTAG-TAP) Controller and verifying using SysteVerilog (SV) and Universal Verification Methodologies (UVM) libraries. Detailed discussion of the design architecture and verification plan is included in the upcoming sections