A study of phase noise and jitter in submicron CMOS phase-locked loop circuits

Phase-locked loops (PLLs) are widely used in communication systems. With the continuously expanding of market for high speed, portable communication devices, low noise CMOS submicron integrated circuit designs of PLL for different applications are in large demand. In this dissertation, phase noise and jitter properties of PLL and its building blocks are investigated both at the physical and system levels. At the physical level, hot carrier effect in submicron MOSFETs has been considered. As one of the most dominant noise sources of PLL, the voltage-controlled oscillator (VCO) is considered when investigating the noise degradation induced by the hot carrier effect. Experimental results of jitter degradation due to hot carrier effects are presented for different ring oscillator types VCOs designed in 0.5 micron n-well CMOS technology. An increase in RMS jitter by 25% and 10% decrease in oscillation frequency of VCO can be observed after 4 hours hot carrier stress. The hot carrier induced noise degradation on PLL is also presented based on the performance degradation in VCO. Simulation results show 40% decrease in VCO gain after 4 hours stress and a 23% decrease in damping factor and loop bandwidth. Moreover, degradation on PLL noise performance includes a left shift peak in phase noise and a 17% increase in RMS jitter. At the system level, noise sources in a PLL system are investigated including the input reference noise, VCO noise and the frequency divider noise. Phase noise prediction method for PLL is developed. Experimental phase noise measurement results on 0.5 micron CMOS PLL systems based on different types of VCOs are in close agreement with the predicted phase noise. Therefore, the phase noise prediction method is verified. On the other hand, a 3 GHz adaptive bandwidth PLL based on LC-VCO is designed in 0.25 micron n-well CMOS technology to investigate the phase noise and jitter performance by varying the loop parameters. By considering the noise simulation results based on the adaptive bandwidth feature and the quality factor of the on-chip inductor, PLL loop parameters can be carefully chosen at the design phase to achieve an optimal noise performance

Analysis of the high frequency substrate noise effects on LC-VCOs

La integració de transceptors per comunicacions de radiofreqüència en CMOS pot quedar seriosament limitada per la interacció entre els seus blocs, arribant a desaconsellar la utilització de un únic dau de silici. El soroll d’alta freqüència generat per certs blocs, com l’amplificador de potencia, pot viatjar pel substrat i amenaçar el correcte funcionament de l’oscil·lador local. Trobem tres raons importants que mostren aquest risc d’interacció entre blocs i que justifiquen la necessitat d’un estudi profund per minimitzar-lo. Les característiques del substrat fan que el soroll d’alta freqüència es propagui m’és fàcilment que el de baixa freqüència. Per altra banda, les estructures de protecció perden eficiència a mesura que la freqüència augmenta. Finalment, el soroll d’alta freqüència que arriba a l’oscil·lador degrada al seu correcte comportament. El propòsit d’aquesta tesis és analitzar en profunditat la interacció entre el soroll d’alta freqüència que es propaga pel substrat i l’oscil·lador amb l’objectiu de poder predir, mitjançant un model, l’efecte que aquest soroll pot tenir sobre el correcte funcionament de l’oscil·lador. Es volen proporcionar diverses guies i normes a seguir que permeti als dissenyadors augmentar la robustesa dels oscil·ladors al soroll d’alta freqüència que viatja pel substrat. La investigació de l’efecte del soroll de substrat en oscil·ladors s’ha iniciat des d’un punt de vista empíric, per una banda, analitzant la propagació de senyals a través del substrat i avaluant l’eficiència d’estructures per bloquejar aquesta propagació, i per altra, determinant l’efecte d’un to present en el substrat en un oscil·lador. Aquesta investigació ha mostrat que la injecció d’un to d’alta freqüència en el substrat es pot propagar fins arribar a l’oscil·lador i que, a causa del ’pulling’ de freqüència, pot modular en freqüència la sortida de l’oscil·lador. A partir dels resultats de l’anàlisi empíric s’ha aportat un model matemàtic que permet predir l’efecte del soroll en l’oscil·lador. Aquest model té el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem. el principal avantatge en el fet de que està basat en paràmetres físics de l’oscil·lador o del soroll, permetent determinar les mesures que un dissenyador pot prendre per augmentar la robustesa de l’oscil·lador així com les conseqüències que aquestes mesures tenen sobre el seu funcionament global (trade-offs). El model ha estat comparat tant amb simulacions com amb mesures reals demostrant ser molt precís a l’hora de predir l’efecte del soroll de substrat. La utilitat del model com a eina de disseny s’ha demostrat en dos estudis. Primerament, les conclusions del model han estat aplicades en el procés de disseny d’un oscil·lador d’ultra baix consum a 2.5GHz, aconseguint un oscil·lador robust al soroll de substrat d’alta freqüència i amb característiques totalment compatibles amb els principals estàndards de comunicació en aquesta banda. Finalment, el model s’ha utilitzat com a eina d’anàlisi per avaluar la causa de les diferències, en termes de robustesa a soroll de substrat, mesurades en dos oscil·ladors a 60GHz amb dues diferents estratègies d’apantallament de l’inductor del tanc de ressonant, flotant en un cas i connectat a terra en l’altre. El model ha mostrat que les diferències en robustesa són causades per la millora en el factor de qualitat i en l’amplitud d’oscil·lació i no per un augment en l’aïllament entre tanc i substrat. Per altra banda, el model ha demostrat ser vàlid i molt precís inclús en aquest rang de freqüència tan extrem.The integration of transceivers for RF communication in CMOS can be seriously limited by the interaction between their blocks, even advising against using a single silicon die. The high frequency noise generated by some of the blocks, like the power amplifier, can travel through the substrate, reaching the local oscillator and threatening its correct performance. Three important reasons can be stated that show the risk of the single die integration. Noise propagation is easier the higher the frequency. Moreover, the protection structures lose efficiency as the noise frequency increases. Finally, the high frequency noise that reaches the local oscillator degrades its performance. The purpose of this thesis is to deeply analyze the interaction between the high frequency substrate noise and the oscillator with the objective of being able to predict, thanks to a model, the effect that this noise may have over the correct behavior of the oscillator. We want to provide some guidelines to the designers to allow them to increase the robustness of the oscillator to high frequency substrate noise. The investigation of the effect of the high frequency substrate noise on oscillators has started from an empirical point of view, on one hand, analyzing the noise propagation through the substrate and evaluating the efficiency of some structures to block this propagation, and on the other hand, determining the effect on an oscillator of a high frequency noise tone present in the substrate. This investigation has shown that the injection of a high frequency tone in the substrate can reach the oscillator and, due to a frequency pulling effect, it can modulate in frequency the output of the oscillator. Based on the results obtained during the empirical analysis, a mathematical model to predict the effect of the substrate noise on the oscillator has been provided. The main advantage of this model is the fact that it is based on physical parameters of the oscillator and of the noise, allowing to determine the measures that a designer can take to increase the robustness of the oscillator as well as the consequences (trade-offs) that these measures have over its global performance. This model has been compared against both, simulations and real measurements, showing a very high accuracy to predict the effect of the high frequency substrate noise. The usefulness of the presented model as a design tool has been demonstrated in two case studies. Firstly, the conclusions obtained from the model have been applied in the design of an ultra low power consumption 2.5 GHz oscillator robust to the high frequency substrate noise with characteristics which make it compatible with the main communication standards in this frequency band. Finally, the model has been used as an analysis tool to evaluate the cause of the differences, in terms of performance degradation due to substrate noise, measured in two 60 GHz oscillators with two different tank inductor shielding strategies, floating and grounded. The model has determined that the robustness differences are caused by the improvement in the tank quality factor and in the oscillation amplitude and no by an increased isolation between the tank and the substrate. The model has shown to be valid and very accurate even in these extreme frequency range.Postprint (published version

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Ionizing radiation effects spectroscopy

The reliability of microelectronics operating in harsh environments is a concern for space systems. Various stresses, such as exposure to ionizing radiation and extreme temperatures can result in performance degradation, transient anomalies, and hard failures. These issues have become evident in recent years with the increasing interest in the use of commercial-off-the-shelf (COTS) electronics in space systems. While COTS parts offer maximum performance, their use results in unavoidable increases in risk. This work presents a noninvasive technique for the measurement of cumulative and transient radiation effects in arbitrary circuits, termed ionizing radiation effects spectroscopy (IRES). IRES identifies radiation effects based on statistical time-frequency analyses of native waveform behavior, thus having a minimal impact on operating performance. The resulting measures are used to identify parametric shifts as well as transient anomalies. IRES, which exploits the subtle characteristics inherent in the waveforms, shows promise for in-situ health monitoring and radiation mitigation

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO