Optimisation of High Reliability Integrated Motor Drives

The development of integrated motor drives (IMDs) with high volumetric power density and reliability are crucial for the continued development and adoption of electric vehicles (EV). The development of the wide bandgap (WBG) devices, especially Silicon Carbide (SiC) MOSFETs, enables new possibilities for traction drive systems. However, to maximise the benefits of SiC, the IMD design process, including passive component selection, control and thermal management should be optimised. This thesis goes through the initial major design steps in SiC power system design, from SiC device analysis and modelling to circuit design and electrothermal simulation of an IMD system. A novel approach to discrete SiC MOSFET selection, using a method of calculating performance based on experimental data, is described. Dynamic behaviour of a family of 1200 V MOSFETs is studied at temperatures up to 175 °C using a double pulse test to show the combined effect of the differences in internal design between MOSFETs with different current ratings. It is observed that the 30 mΩ MOSFET had a 24 % higher switching loss than a 140 mΩ at a 30 A load current. The study then goes on to compare the effect of switching frequency, paralleling of MOSFETs and the device type used to demonstrate the inverter design with the lowest power losses, which will equate to low temperatures and high lifetime. The novel methodology can find the optimal choice of MOSFET from the family, and number required through paralleling, for a circuit when given the load current, temperature and switching. Understanding the device interdependencies in a single family is utilised to also predict the relative performance between SiC MOSFETs from different manufacturers. An axial-flux permanent magnet synchronous motor (PMSM) driven by a three-phase SiC inverter is simulated in PLECS using experimentally validated MOSFET models chosen by the device selection methodology. Electrothermal analysis shows the influence of switching frequency, temperature, MOSFETs paralleling and DC-link capacitance on voltage ripple, total harmonic distortion, efficiency and MOSFET loss and temperature profiles. With a 60 % decrease in THD and 50 % increase in maximum MOSFET junction temperature when switching frequency is increased from 10 to 100 kHz. The high-temperature stress on the semiconductors due to close proximity with the ma- chine stator means reliability is an important consideration that is yet to be fully investigated in IMD optimisations. This study uses a lifetime model specific to the transistor package TO-247 in reliability optimisation for IMD for the first time. It requires detailed MOSFET simulation outputs to provide a highly accurate lifetime for discrete SiC MOSFETs. Both single and multi-objective optimisations of the volume and lifetime of the three- phase inverter are presented. The single objective optimisation demonstrates the minimum volume and the corresponding switching frequency and lifetime when between three and six MOSFETs are paralleled at a temperature range between 50 and 150 °C. Design constraints were set limiting the feasible switching frequency range to between 13 kHz because of THD and 118 kHz because of efficiency limits, corresponding to required DC-link capacitors of 520 and 55 μF respectively. Increases in temperature were found to further limit the maximum switching frequency and therefore increase the minimum volume of the inverter. A Pareto front identifies a range of possible solutions for the volume and lifetime of an inverter with six paralleled MOSFETs through the multi-objective objective procedure. Further analysis of these possible solutions identified a single optimal solution for the system, using a DC-link capacitance of 190 μF at 45 kHz, giving a combined volume of the capacitor and MOSFETs of 440 cm3 and a lifetime of 12,000 hours. Finally, the electrothermal analysis of a dual inverter driving a symmetric six-phase PMSM is presented with the benefits of modular multi-phase systems in IMDs summarised. Effect on performance of lower per-phase current, interleaving strategies and fault tolerance are analysed and compared to equivalent three-phase systems, for 60 kW and 120 kW operation. A novel method for lifetime prediction of systems with paralleled MOSFETs or fault tolerance capabilities considering incremental damage is developed based on TO-247 lifetime calculations from PLECS simulation, and component-level reliability profiles using Monte Carlo analysis. The dual inverter is used to model the system and implements control schemes for both single-phase and single inverter failure while maintaining the 4000 rpm and 140 Nm speed and torque requirements. A twofold increase in B10 lifetime of is observed when the effect of paralleled SiC MOSFETs prevents immediate system failure in a three-phase inverter. A computational fluid dynamics (CFD) and 3D finite element thermal model are designed to study the inverter behaviour based on the thermal analysis of its shared cooling plate with a 300 mm diameter axial flux PMSM. Concentric layout designs minimise the variation of junction temperatures to 5 °C and the effect of the flow rate and temperature of the coolant in the PMSM cold plate is presented between 5 and 30 l/min. The multi-objective optimisation procedure used to compare the dual inverter demonstrated it outperformed the three-phase inverter with 15 % smaller required DC-link capacitance, higher efficiency and increased lifetime in part due to its fault-tolerant nature. The optimal dual inverter considering the design constraints consists of four 40 μF KEMET film capacitors operating with a switching frequency of 46 kHz giving an inverter volume of 300 cm3 and a lifetime of 16.3 years, assuming 1000 hours of operation annually

A road map for reliable power electronics for more electric aircraft

The gradual evolution from hydro-pneumatic to electrical disposition of power in aircraft has placed stringent requirements on the reliability of power electronic components in current and future aerospace applications. This paper examines the prevalent state-of-the-art in power electronics and provides an analytical overview of power electronics in More Electric Aircraft (MEA) vis-à-vis the generation and distribution of power within these aircraft. The types of power devices currently employed for multiple conversion topologies are analysed and weighed according to their respective reliability characteristics. Beginning with an in-depth review of failure modes in the currently available devices, the paper highlights the salient emerging state-of-the-art Wide Band Gap (WBG) technologies such as Gallium Nitride (GaN) and Silicon Carbide (SiC) and draws an extensive comparison with their Silicon counterparts. A comprehensive examination of techniques employed for the estimation of the reliability of WBG power devices has revealed a number of areas that merit due consideration. For instance, the physics-based models that have been developed to assess the operational lifetime of silicon-based devices for given failure modes require revamping in light of the new materials and the unique electrical and physical characteristics the WBG devices possess. Similarly, the condition monitoring techniques, with respect to the primary and secondary parameters, require further investigation to determine highly representative feature vectors that best describe the degradation within these devices. More significantly, optimisation of the proposed techniques for the health assessment of these devices needs to be pursued through the optimal use of vital parameters. Keeping these critical findings in perspective, a road map highlighting various avenues for power electronics optimisation in MEA is put forth to apprise the aerospace fraternity of its growing significance

Multilevel inverters for renewable energy systems

Voltage source inverters have become widely used in the last decade primarily due to the fact that the dangers and limitations of relying on fossil fuel based power generation have been seen and the long term effects felt especially with regards to climate change. Policies and targets have been implemented such as from the United Nations climate change conference (COPxx) concerning human activities that contribute to global warming from individual countries. The most effective way of reducing these greenhouse gases is to turn to renewable energy sources such as the solar, wind etc instead of coal. Converters play the crucial role of converting the renewable source dc power to ac single phase or multiphase. The advancement in research in renewable energy sources and energy storage has made it possible to do things more efficiently than ever before. Regular or 2 level inverters are adequate for low power low voltage applications but have drawbacks when being used in high power high voltage applications as switching components have to be rated upwards and also switch between very high potential differences. To lessen the constraints on the switching components and to reduce the filtering requirements, multilevel inverters (MLI's) are preferred over two level voltage source inverters (VSI's). This thesis discusses the implementation of various types of MLI's and compares four different pulse width modulation (pwm) techniques that are often used in MLI under consideration: three, five, seven and nine level inverters. Harmonic content of the output voltage is recorded across a range of modulation indices for each of the three popular topologies in literature. Output from the inverter is filtered using an L only and an LC filter whose design techniques are presented. A generalized prediction algorithm using machine learning techniques to give the value of the expected THD as the modulation index is varied for a specific topology and PWM switching method is proposed in this study. Simulation and experimental results are produced in five level form to verify and validate the proposed algorithm

High power microwave interference effects on analog and digital circuits in IC's

Microwave or electromagnetic interference (EMI) can couple into electronic circuits and systems intentionally from high power microwave (HPM) sources or unintentionally due to the proximity to general electromagnetic (EM) environments, and cause "soft" reversible upsets and "hard" irreversible failures. As scaling-down of device feature size and bias voltage progresses, the circuits and systems become more susceptible to the interference. Thus, even low power interference can disrupt the operation of the circuits and systems. Furthermore, it is reported that even electronic systems under high level of shielding can be upset by intentional electromagnetic interference (IEMI), which has been drawing a great deal of concern from both the civil and military communities, but little has been done in terms of systematic study and investigation of these effects on IC circuits and devices. We have investigated the effects of high power microwave interference on three levels, (a) on fundamental single MOSFET devices, (b) on basic CMOS IC inverters and cascaded inverters, and (c) on a representative large IC timer circuit for automotive applications. We have studied and identified the most vulnerable static and dynamic parameters of operation related to device upsets. Fundamental upset mechanisms in MOSFETs and CMOS inverters and their relation to the characteristics of microwave interference (power, frequency, width, and period) and the device properties such as size, mobility, dopant concentration, and contact resistances, were investigated. Critical upsets in n-channel MOSFET devices resulting in loss of amplifier characteristics, were identified for the power levels above 10dBm in the frequency range between 1 and 20 GHz. We have found that microwave interference induced excess charges are responsible for the upsets. Upsets in the static operation of CMOS inverters such as noise margins, output voltages, power dissipation, and bit-flip errors were identified using a load-line characteristic analysis. We developed a parameter extraction method that can predict the dynamic operation of inverters under microwave interference from DC load-line characteristics. Using the method, the effects of microwave interference on propagation delays, output voltage swings, and output currents as well as their relation to device scaling, were investigated. Two new critical hard error sources in MOSFETs and CMOS inverters regarding power dissipation and power budget disruption were found. EMI hardened design for digital circuits has been proposed to mitigate the stress on the devices, the contacts, and the interconnects. We found important new bit-flip and latch-up errors under pulsed microwave interference, which demonstrated that the excess charge effects are due to electron-hole pair generation under microwave interference. We proposed a theory of excess charge effects and obtained good agreement of our excess charge model with our experimental results. Further work is proposed to improve the vulnerabilities of integrated circuits

Source reconstruction in near field scanning for RFI application

This research is divided into three major topics. The first topic, mechanical magnetic field generator for communication in the ULF range, is discussed in the first paper. The second topic, source reconstruction in near field scanning for RFI application, is discussed over the course of two papers. The third topic, analysis of imbalanced 2 or 3 Wire VHF LISN, is discussed in the last two papers. In the first topic, the possibility to use a mechanical system (a rotating magnet) as a source (generator or antenna combined) of the ULF magnetic field is investigated. Ultralow frequency (ULF) communication systems have advantage over the RF systems in lossy media such as soil or water. A conventional way to create ULF fields is to use coils. It is demonstrated that the mechanical sources have advantage over coils in terms of occupied volume or dissipated power and can be a viable alternative for low-size, weight, and power applications. In the second topic, methods are presented to predict the high-frequency near electric- and magnetic- fields from a component using a Method of Moment (MoM) approach. Additionally, the impact of three major sources of error in near field scans: random measurement noise, cross field coupling, and position error, is investigated on field prediction. A clear decision-making process with examples is provided to guide the user toward selection of the best representation. In the third topic, an analysis of an imbalanced two- or three-wire VHF LISN is conducted in terms of its mode conversion and termination impedance. It is demonstrated that an imbalanced termination impedance provides a specified degree of conversion from differential- to common-mode, which can lead to more representative radiated emission test results --Abstract, page iv

Accurate modeling techniques for power delivery

“Power delivery is essential in electronic systems to provide reliable power from voltage sources to load devices. Driven by the ambitious user demands and technology evolutions, the power delivery design is posed serious challenges. In this work, we focus on modeling two types of power delivery paths: the power distribution network (PDN) and the wireless power transfer (WPT) system. For the modeling of PDN, a novel pattern-based analytical method is proposed for PCB-level PDN impedance calculations, which constructs an equivalent circuit with one-to-one correspondences to the PCB’s physical structure. A practical modeling methodology is also introduced to optimize the PDN design. In addition, a topology-based behavior model is developed for the current-mode voltage regulator module (VRM). This model includes all the critical components in the power stage, the voltage control loop, and the current control loop of a VRM device. A novel method is also proposed to unify the modeling of the continuous and discontinuous conduction modes for transient load responses. Cascading the proposed VRM model with the PCB-level PDN model enables a combined PDN analysis, which is much needed for modern PDN designs. For the modeling of WPT system, a system-level model is developed for both efficiency and power loss of all the blocks in WPT systems. A rectifier characterization method is also proposed to obtain the accurate load impedance. This model is capable of deriving the power capabilities for both the fundamental and higher order harmonics. Based on the system model, a practical design methodology is introduced to simultaneously optimize multiple system parameters, which greatly accelerates the design process”--Abstract, page iv

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

The Characterization of a CMOS Radiation Hardened-by-Design Circuit Technique

This thesis presents the analysis, implementation and testing of a circuit-level radiation hardened-by-design (RHBD) technique first presented in [1]. Radiation effects heavily influence the cost and design of electronics bound for radiation-rich environments such as in nuclear reactors or space. The circuit-level RHBD technique is presented as a cost-effective way to mitigate total-ionizing dose (TID) radiation in digital complementary metal-oxide-semiconductor (CMOS) transistor circuits. These claims are analyzed and experimentally tested. Devices from a relatively old and a newer semiconductor fabrication process are tested to investigate the impact of device scaling on the RHBD technique’s effectiveness. A rad-tolerant frequency synthesizer that implements this technique is discussed. Challenges in the project included implementing efficient testing procedures at the radiation test facilities. Testing time was limited and in-situ­ test methodologies utilizing LabView programs were used effectively

Double smart energy harvesting system for self-powered industrial IoT

312 p. 335 p. (confidencial)Future factories would be based on the Industry 4.0 paradigm. IndustrialInternet of Things (IIoT) represent a part of the solution in this field. Asautonomous systems, powering challenges could be solved using energy harvestingtechnology. The present thesis work combines two alternatives of energy input andmanagement on a single architecture. A mini-reactor and an indoor photovoltaiccell as energy harvesters and a double power manager with AC/DC and DC/DCconverters controlled by a low power single controller. Furthermore, theaforementioned energy management is improved with artificial intelligencetechniques, which allows a smart and optimal energy management. Besides, theharvested energy is going to be stored in a low power supercapacitor. The workconcludes with the integration of these solutions making IIoT self-powered devices.IK4 Teknike