Error modeling, self-calibration and design of pipelined analog to digital converters

Typescript (photocopy).As the field of signal processing accelerates toward the use of high performance digital techniques, there is a growing need for increasingly fast and accurate analog to digital converters. Three highly visible examples of this trend originated in the last decade. The advent of the compact disc revolutionized the way high-fidelity audio is stored, reproduced, recorded and processed. Digital communication links, fiber optic cables and in the near future ISDN networks (Integrated Services Digital Network) are steadily replacing major portions of telephone systems. Finally, video-conferencing, multi-media computing and currently emerging high definition television (HDTV) systems rely more and more on real-time digital data compression and image enhancing techniques. All these applications rely on analog to digital conversion. In the field of digital audio, the required conversion accuracy is high, but the conversion speed limited (16 bits, 2 x 20 kHz signal bandwidth). In the field of image processing, the required accuracy is less, but the data conversion speed high (8-10 bits, 5-20MHz bandwidth). New applications keep pushing for increasing conversion rates and simultaneously higher accuracies. This dissertation discusses new analog to digital converter architectures that could accomplish this. As a consequence of the trend towards digital processing, prominent analog designers throughout the world have engaged in very active research on the topic of data conversion. Unfortunately, literature has not always kept up. At the time of this writing, it seemed rather difficult to find detailed fundamental publications about analog to digital converter design. This dissertation represents a modest attempt to remedy this situation. It is hoped that anyone with a back-ground in analog design could go through this work and pick up the fundamentals of converter operation, as well as a number of more advanced design techniques

High-speed interferometric FBG interrogator with dynamic and absolute wavelength measurement capability

A passive, interferometric wavelength demodulation technique has been extended to measure the absolute wavelengths of a multiplexed array of fiber Bragg grating sensors. The scheme retains its original strain resolution of 10 nε/√{Hz}. A proof-of-concept interrogation system was able to determine the absolute wavelength of Bragg peaks to within 20 pm (17 με). Static and dynamic Bragg grating strains were accurately demodulated in both absolute and relative wavelength measurement modes. This demonstration indicates that interferometric techniques are able to provide absolute, static and dynamic measurements of strain within a single platform

Performance of the LHCb vertex locator

The Vertex Locator (VELO) is a silicon microstrip detector that surrounds the proton-proton interaction region in the LHCb experiment. The performance of the detector during the first years of its physics operation is reviewed. The system is operated in vacuum, uses a bi-phase CO2 cooling system, and the sensors are moved to 7 mm from the LHC beam for physics data taking. The performance and stability of these characteristic features of the detector are described, and details of the material budget are given. The calibration of the timing and the data processing algorithms that are implemented in FPGAs are described. The system performance is fully characterised. The sensors have a signal to noise ratio of approximately 20 and a best hit resolution of 4 μm is achieved at the optimal track angle. The typical detector occupancy for minimum bias events in standard operating conditions in 2011 is around 0.5%, and the detector has less than 1% of faulty strips. The proximity of the detector to the beam means that the inner regions of the n+-on-n sensors have undergone space-charge sign inversion due to radiation damage. The VELO performance parameters that drive the experiment's physics sensitivity are also given. The track finding efficiency of the VELO is typically above 98% and the modules have been aligned to a precision of 1 μm for translations in the plane transverse to the beam. A primary vertex resolution of 13 μm in the transverse plane and 71 μm along the beam axis is achieved for vertices with 25 tracks. An impact parameter resolution of less than 35 μm is achieved for particles with transverse momentum greater than 1 GeV/c

Characterization of a 12-bit pipeline analog to digital converter

This thesis presents the characterization of the 12-bit pipeline analog-to-digital converter (ADC) designed by Mark Hale, Ph.D. graduate from the University of Tennessee. An overview of the pipeline ADC architecture is discussed first, and then the specifics of the testing procedure and results are detailed. The differential nonlinearity (DNL), integral nonlinearity (INL), DC offset error, and gain error for the pipeline ADC are the DC characteristics of interest. The DC characterization was performed in order to analyze the linearity of the ADC output over the analog input range. Additionally, the DNL and INL results were used to determine if the ADC exhibited undesirable effects, such as missed codes. The characterization was performed at room temperature using differential sinusoidal inputs. Labview was utilized to efficiently gather the digital output levels of the ADC, and Matlab was employed to compute the characteristics of the tested ADC. During the testing process several difficulties were encountered. Characterization results were negatively impacted by the presence of noise both at the output of the sample-and-hold and on the supply rails. Through iterative testing, the results improved. However, the effective number of bits for the tested ADC did not attain the desired 12-bits

Software Defined Radio Implementation of Carrier and Timing Synchronization for Distributed Arrays

The communication range of wireless networks can be greatly improved by using distributed beamforming from a set of independent radio nodes. One of the key challenges in establishing a beamformed communication link from separate radios is achieving carrier frequency and sample timing synchronization. This paper describes an implementation that addresses both carrier frequency and sample timing synchronization simultaneously using RF signaling between designated master and slave nodes. By using a pilot signal transmitted by the master node, each slave estimates and tracks the frequency and timing offset and digitally compensates for them. A real-time implementation of the proposed system was developed in GNU Radio and tested with Ettus USRP N210 software defined radios. The measurements show that the distributed array can reach a residual frequency error of 5 Hz and a residual timing offset of 1/16 the sample duration for 70 percent of the time. This performance enables distributed beamforming for range extension applications.Comment: Submitted to 2019 IEEE Aerospace Conferenc

The first version Buffered Large Analog Bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors

Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a cost-effective, compact and low-power way. A first version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. A prototype has been designed and fabricated with 65k deep sampling at multi-GSa/s operation. We present test results and directions for future evolution of this sampling technique.Comment: 15 pages, 26 figures; revised, accepted for publication in NIM