Investigation into a GPS time pulse radiator for testing time-stamp accuracy of a radio telescope

The MeerKAT radio telescope in South Africa is required to tag the arrival time of a signal to within 10 ns of Coordinated Universal Time (UTC). The telescope has a local atomic clock ensemble and uses satellite based remote clock comparison techniques to compare the telescope time to UTC. The master clock timing edge is distributed to each telescope antenna via an optical fibre precise time transfer. Although the timing accuracy of the telescope time was measured internally by the telescope, there is a need for an independent method to verify how well each antenna and its associated processing stages are aligned to UTC. A portable GNSS time-pulse radiator (GTR) device for testing the time-stamp accuracy was developed. The GTR was calibrated at the National Metrology Institute of South Africa and laboratory characterisation tests measured its RF timing pulse to be 1.32 ± 0.100 µs ahead of the UTC second. The telescope’s time and frequency reference clock ensemble consists of two hydrogen masers, an ultrastable crystal and GPS disciplined Rubidium clocks. During operation, the GTR radiates a broadband GPS time synchronised RF timing signal at a known distance from the telescope antennas and the corresponding timestamps were compared to the expected value. Recent GTR timing tests performed on one of the MeerKAT antennas showed that the telescope’s generated timestamps associated with the GTR’s RF timing signal coincided with the expected delay of approximately 16 ± 0.1 µs measured from an antenna 4.8 km away from the telescope’s master clock transmitter. Ultimately we used the GTR to verify that the telescope time and UTC were aligned to within 100 ns. Future work is planned to improve the profile of the transmitted signal and timing critical hardware in order to reduce the GTR’s error budget

Study of spacecraft direct readout meteorological systems

Characteristics are defined of the next generation direct readout meteorological satellite system with particular application to Tiros N. Both space and ground systems are included. The recommended space system is composed of four geosynchronous satellites and two low altitude satellites in sun-synchronous orbit. The goesynchronous satellites transmit to direct readout ground stations via a shared S-band link, relayed FOFAX satellite cloud cover pictures (visible and infrared) and weather charts (WEFAX). Basic sensor data is transmitted to regional Data Utilization Stations via the same S-band link. Basic sensor data consists of 0.5 n.m. sub-point resolution data in the 0.55 - 0.7 micron spectral region, and 4.0 n.m. resolution data in the 10.5 - 12.6 micron spectral region. The two low altitude satellites in sun-synchronous orbit provide data to direct readout ground stations via a 137 MHz link, a 400 Mhz link, and an S-band link

Silicon Photonic Subsystems for Inter-Chip Optical Networks

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s

Construction and commissioning of a technological prototype of a high-granularity semi-digital hadronic calorimeter

A large prototype of 1.3m3 was designed and built as a demonstrator of the semi-digital hadronic calorimeter (SDHCAL) concept proposed for the future ILC experiments. The prototype is a sampling hadronic calorimeter of 48 units. Each unit is built of an active layer made of 1m2 Glass Resistive Plate Chamber(GRPC) detector placed inside a cassette whose walls are made of stainless steel. The cassette contains also the electronics used to read out the GRPC detector. The lateral granularity of the active layer is provided by the electronics pick-up pads of 1cm2 each. The cassettes are inserted into a self-supporting mechanical structure built also of stainless steel plates which, with the cassettes walls, play the role of the absorber. The prototype was designed to be very compact and important efforts were made to minimize the number of services cables to optimize the efficiency of the Particle Flow Algorithm techniques to be used in the future ILC experiments. The different components of the SDHCAL prototype were studied individually and strict criteria were applied for the final selection of these components. Basic calibration procedures were performed after the prototype assembling. The prototype is the first of a series of new-generation detectors equipped with a power-pulsing mode intended to reduce the power consumption of this highly granular detector. A dedicated acquisition system was developed to deal with the output of more than 440000 electronics channels in both trigger and triggerless modes. After its completion in 2011, the prototype was commissioned using cosmic rays and particles beams at CERN.Comment: 49 pages, 41 figure

JUNO Conceptual Design Report

The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine the neutrino mass hierarchy using an underground liquid scintillator detector. It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants in Guangdong, China. The experimental hall, spanning more than 50 meters, is under a granite mountain of over 700 m overburden. Within six years of running, the detection of reactor antineutrinos can resolve the neutrino mass hierarchy at a confidence level of 3-4$\sigma$, and determine neutrino oscillation parameters $\sin^2\theta_{12}$, $\Delta m^2_{21}$, and $|\Delta m^2_{ee}|$ to an accuracy of better than 1%. The JUNO detector can be also used to study terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard Model. The central detector contains 20,000 tons liquid scintillator with an acrylic sphere of 35 m in diameter. $\sim$17,000 508-mm diameter PMTs with high quantum efficiency provide $\sim$75% optical coverage. The current choice of the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of detected photoelectrons per MeV is larger than 1,100 and the energy resolution is expected to be 3% at 1 MeV. The calibration system is designed to deploy multiple sources to cover the entire energy range of reactor antineutrinos, and to achieve a full-volume position coverage inside the detector. The veto system is used for muon detection, muon induced background study and reduction. It consists of a Water Cherenkov detector and a Top Tracker system. The readout system, the detector control system and the offline system insure efficient and stable data acquisition and processing.Comment: 328 pages, 211 figure

On-chip signaling techniques for high-speed Serdes transceivers

The general goal of the VLSI technology is to produce very fast chips with very low power consumption. The technology scaling along with increasing the working frequency had been the perfect solution, which enabled the evolution of electronic devices in the 20th century. However, in deep sub-micron technologies, the on-chip power density limited the continuous increment in frequency, which led to another trend for designing higher performance chips without increasing the working speed. Parallelism was the optimum solution, and the VLSI manufacturers began the era of multi-core chips. These multi-core chips require a full inter-core network for the required communication. These on-chip links were conventionally parallel. However, due to reverse scaling in modern technologies, parallel signaling is becoming a burden due to the very large area of needed interconnects. Also, due to the very high power due to the tremendous number of repeaters, in addition to cross talk issues. As a solution, on-chip serial communication was suggested. It will solve all the previous issues, but it will require very high speed circuits to achieve the same data rates. This thesis presents two full SerDes transceiver designs for on-chip high speed serial communication. Both designs use long lossy on-chip differential interconnects with capacitive termination. The first design uses a 3-level self-timed signaling technique. This signaling technique is totally jitter-insensitive, since both of the data and clock are extracted at the receiver from the same signal. A new encoding and driving technique is designed to enable the transmitter to work at a frequency equal to the data rate, which is half of the frequency of the previous designs, along with achieving the same data rate. Also, this design generates the third voltage level without the need of an external supply. This design is very tolerant to any possible variations, such as PVT variations or the input clock\u27s duty cycle variations. This transceiver is prepared for tape-out in UMC 0.13μm CMOS technology in June 2014. The second design uses a new 3-level signaling technique; the proposed technique uses a frequency of only half the data rate, which totally relaxes the full transceiver design. The new technique is also self-timed enabling the extraction of both the data, and the clock from the same signal. New encoders and decoders are designed, and a new architecture for a 3-level inverter is presented. This transceiver achieves very high data rates. This new design is expected to be taped-out using the GF 65nm CMOS technology in August 2014

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

Construction of FASR subsystem testbed and application for solar burst trajectories and RFI study

The construction of the Frequency Agile Solar Radiotelescope (FASR) Subsystem Testbed (FST) and observational results are described. Three antennas of Owens Valley Solar Array (OVSA) have been upgraded with newly designed, state of art technology. The 1-9 GHz RF signal from the antenna feed is transmitted via broadband (45 MHz-9.5 GHz) optical fiber links to the control room. The RF is then downconverted to a 500 MHz, single-sideband signal that can be tuned across the 1-9 GHz RF band. The data are sampled with an 8-bit, 1 GHz sampling-rate digitizer, and further saved to a computer hard disk. The full-resolution time-domain data thus recorded are then correlated through offline software to provide phase and amplitude spectra. An important feature of this approach is that the data can be reanalyzed multiple times with different digital signal-processing techniques (e.g., different bit-sampling, windowing, and RFI excision methods) to test the effects of different designs. As a prototype of the FASR system, FST provides the opportunity to study the design, calibration and interference-avoidance requirements of FASR. In addition, FST provides, for the first time, the ability to perform broadband spectroscopy of the Sun with high spectral, temporal and moderate spatial resolution. With this three-element interferometer, one has the ability to determine the location of simple sources with spectrograph-like time and frequency resolution. The large solar flare of 2006 December 6 was detected by the newly constructed FASR Subsystem Testbed, which is operating on three antennas of Owens Valley Solar Array. This record-setting burst produced an especially fine set of fiber bursts--so-called intermediate-drift bursts that drift from high to low frequencies over 6-10 s. According to a leading theory (Kuijpers 1975), the fibers are generated by packets of whistler waves propagating along a magnetic loop, which coalesce with Langmuir waves to produce escaping electromagnetic radiation in the decimeter band. With this three element interferometer, for the first time fiber burst source locations can be determined relative to the background even though the absolute location is still unkown for the lack of phase calibration information. The radio information over a 500 MHz band (1.0-1.5 GHz) was used to determine the trajectories of the bursts. Since the digital data are recorded with full resolution and processed offline, a key advantage of it is that one can process the data in different ways in order to simulate and test hardware implementations. FST data provides a unique testbed for studying methods of RFI excision. RFI is observed to be present in every one of the 500 MHz bands, and the high time and frequency resolution provided by FST allows one to characterize it in great detail. The use of time-domain kurtosis, and a variant of the kurtosis method in the frequency domain were explored to identify the presence of RFI and flag bad channels in simulated real time (i.e., we play back the raw, full-resolution recorded data and flag the bad channels during play-back just as a real-time system would do). The ability to select alternate RFI excision algorithms during play-back allows one to compare algorithms on an equal basis. From the same data set, the two kurtosis (time domain and frequency domain) RFI excision algorithms were compared. The results are compared quantitatively to show that the spectral kurtosis is more effective than time domain kurtosis algorithm for detecting the RFI contamination, as expected from theoretical considerations

Trade-off analysis of modes of data handling for earth resources (ERS), volume 1

Data handling requirements are reviewed for earth observation missions along with likely technology advances. Parametric techniques for synthesizing potential systems are developed. Major tasks include: (1) review of the sensors under development and extensions of or improvements in these sensors; (2) development of mission models for missions spanning land, ocean, and atmosphere observations; (3) summary of data handling requirements including the frequency of coverage, timeliness of dissemination, and geographic relationships between points of collection and points of dissemination; (4) review of data routing to establish ways of getting data from the collection point to the user; (5) on-board data processing; (6) communications link; and (7) ground data processing. A detailed synthesis of three specific missions is included

Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important