Software simulation of MC68000

The introduction of the Motorola MC68000 family of microprocessors ushered in a new era of microprocessors. These are single-chip microprocessors designed to function as the central processing units of sophisticated computer systems. The prime objective of this thesis work is to develop a simulator for the MC68000 microprocessor mainly for educational purposes. The simulator would help in any test or research work utilizing 68000 assembly programs in the future. Most of the instructions in the 68000 family are implemented. Both the user mode and supervisory mode programs can be written and run against the simulator. Besides supporting most of the MC68000 features the simulator also has additional features to help debugging

OBVIAS: A visual interactive editor/assembler on the Corvus Concept Personal Workstation

Thesis (M.S.)--University of Kansas, Computer Science, 1984

Software implemented fault tolerance for microprocessor controllers: fault tolerance for microprocessor controllers

It is generally accepted that transient faults are a major cause of failure in micro processor systems. Industrial controllers with embedded microprocessors are particularly at risk from this type of failure because their working environments are prone to transient disturbances which can generate transient faults. In order to improve the reliability of processor systems for industrial applications within a limited budget, fault tolerant techniques for uniprocessors are implemented. These techniques aim to identify characteristics of processor operation which are attributed to erroneous behaviour. Once detection is achieved, a programme of restoration activity can be initiated. This thesis initially develops a previous model of erroneous microprocessor behaviour from which characteristics particular to mal-operation are identified. A new technique is proposed, based on software implemented fault tolerance which, by recognizing a particular behavioural characteristic, facilitates the self-detection of erroneous execution. The technique involves inserting detection mechanisms into the target software. This can be quite a complex process and so a prototype software tool called Post-programming Automated Recovery UTility (PARUT) is developed to automate the technique's application. The utility can be used to apply the proposed behavioural fault tolerant technique for a selection of target processors. Fault injection and emulation experiments assess the effectiveness of the proposed fault tolerant technique for three application programs implemented on an 8, 16, and 32- bit processors respectively. The modified application programs are shown to have an improved detection capability and hence reliability when the proposed fault tolerant technique is applied. General assessment of the technique cannot be made, however, because its effectiveness is application specific. The thesis concludes by considering methods of generating non-hazardous application programs at the compilation stage, and design features for incorporation into the architecture of a microprocessor which inherently reduce the hazard, and increase the detection capability of the target software. Particular suggestions are made to add a 'PARUT' phase to the translation process, and to orientate microprocessor design towards the instruction opcode map

Aerospace Applications of Microprocessors

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed

Optimal kernel development for real-time communications

The purpose of this research is to develop an optimal kernel which would be used in a real-time engineering and communications system. Since the application is a real-time system, relevant real-time issues are studied in conjunction with kernel related issues. The emphasis of the research is the development of a kernel which would not only adhere to the criteria of a real-time environment, namely determinism and performance, but also provide the flexibility and portability associated with non-real-time environments. The essence of the research is to study how the features found in non-real-time systems could be applied to the real-time system in order to generate an optimal kernel which would provide flexibility and architecture independence while maintaining the performance needed by most of the engineering applications. Traditionally, development of real-time kernels has been done using assembly language. By utilizing the powerful constructs of the C language, a real-time kernel was developed which addressed the goals of flexibility and portability while still meeting the real-time criteria. The implementation of the kernel is carried out using the powerful 68010/20/30/40 microprocessor based systems

Enhanced performance simulation of diesel engines

SIGLEAvailable from British Library Document Supply Centre- DSC:DX90577 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

The integrity of serial data highway systems

The Admiralty Surface Weapons Establishment (ASWE) have developed a Local Area Network System. This thesis describes the development of a replacement for this LAN system, based around 16 bit microprocessor hosts, as opposed to the minicomputers currently used. This change gave a substantial reduction in size, and allowed the new system to be installed on a ship and tested under operational conditions. Analysis of the data collected during the tests gave performance information on the ASWE system. The performance of this LAN is compared to that of other leading types of LAN. The design of a portable network controller/ monitor unit is presented, which may be manufactured as a standard controller for the ASWE Serial Highway

Implementing run-time support for Modula-2

Call number: LD2668 .R4 CMSC 1988 L5Master of ScienceComputing and Information Science