Selection of a new hardware and software platform for railway interlocking

The interlocking system is one of the main actors for safe railway transportation. In most cases, the whole system is supplied by a single vendor. The recent regulations from the European Union direct for an “open” architecture to invite new game changers and reduce life-cycle costs. The objective of the thesis is to propose an alternative platform that could replace a legacy interlocking system. In the thesis, various commercial off-the-shelf hardware and software products are studied which could be assembled to compose an alternative interlocking platform. The platform must be open enough to adapt to any changes in the constituent elements and abide by the proposed baselines of new standardization initiatives, such as ERTMS, EULYNX, and RCA. In this thesis, a comparative study is performed between these products based on hardware capacity, architecture, communication protocols, programming tools, security, railway certifications, life-cycle issues, etc

UNE PLATEFORME RADIO LOGICIELLE OUVERTE POUR LES SYSTÈMES 3G+

This paper describes a software-radio architecture developed for providing real-time wide-band radio communication capabilities in a form attractive for advanced 3G systems research. It is currently being used to implement signaling methods and protocols similar, but not limited to, evolving 3G radio standards (e.g. umts, cdma2000). An overview of the hardware system is provided along with example software implementations on both high-perfo-mance DSP systems and conventional microprocessor

Design, Implementation and Verification Using UML-RT in GSM Radio Base Station 2000

This work deals with the issue of implementing a UML-RT standard, one of the latest notations for object oriented specification and design, in the developing-process of new real-time software for Radio Base Stations in the 2000 series at Ericsson. UML-RT is the real-time extension of the Unified Modeling Language (UML). The thesis investigates the design-, implementation- and verification-problems that exist when combining the current RT functions, Multi Platform Support, with the UML-RT tool, ObjecTime Developer. We describe UML, look at the advantages and disadvantages of using UML-RT tools and investigate current and future possibilities in ObjecTime Developer

Quarantine-mode based live patching for zero downtime safety-critical systems

150 p.En esta tesis se presenta una arquitectura y diseño de software, llamado Cetratus, que permite las actualizaciones en caliente en sistemas críticos, donde se efectúan actualizaciones dinámicas de los componentes de la aplicación. La característica principal es la ejecución y monitorización en modo cuarentena, donde la nueva versión del software es ejecutada y monitorizada hasta que se compruebe la confiabilidad de esta nueva versión. Esta característica también ofrece protección contra posibles fallos de software y actualización, así como la propagación de esos fallos a través del sistema. Para este propósito, se emplean técnicas de particionamiento. Aunque la actualización del software es iniciada por el usuario Updater, se necesita la ratificación del auditor para poder proceder y realizar la actualización dinámica. Estos usuarios son autenticados y registrados antes de continuar con la actualización. También se verifica la autenticidad e integridad del parche dinámico. Cetratus está alineado con las normativas de seguridad funcional y de ciber-seguridad industriales respecto a las actualizaciones de software.Se proporcionan dos casos de estudio. Por una parte, en el caso de uso de energía inteligente, se analiza una aplicación de gestión de energía eléctrica, compuesta por un sistema de gestión de energía (BEMS por sus siglas en ingles) y un servicio de optimización de energía en la nube (BEOS por sus siglas en ingles). El BEMS monitoriza y controla las instalaciones de energía eléctrica en un edificio residencial. Toda la información relacionada con la generación, consumo y ahorro es enviada al BEOS, que estima y optimiza el consumo general del edificio para reducir los costes y aumentar la eficiencia energética. En este caso de estudio se incorpora una nueva capa de ciberseguridad para aumentar la ciber-seguridad y privacidad de los datos de los clientes. Específicamente, se utiliza la criptografía homomorfica. Después de la actualización, todos los datos son enviados encriptados al BEOS.Por otro lado, se presenta un caso de estudio ferroviario. En este ejemplo se actualiza el componente Euroradio, que es la que habilita las comunicaciones entre el tren y el equipamiento instalado en las vías en el sistema de gestión de tráfico ferroviario en Europa (ERTMS por sus siglas en ingles). En el ejemplo se actualiza el algoritmo utilizado para el código de autenticación del mensaje (MAC por sus siglas en inglés) basado en el algoritmo de encriptación AES, debido a los fallos de seguridad del algoritmo actual

Software Defined Radio Platform for Cognitive Radio: Design and Hierarchical Management

ISBN 978-953-307-274-6Cognitive radio (CR) and/or Software Defined Radio (SDR) inherently require multiband and multi-standard wireless circuit. A SDR is a communications device whose functionality is defined in software. Defining the radio behaviour in software removes the need for hardware alterations during a technology upgrade. A promised open architecture platform for SDR is proposed in this chapter. The platform consists of reconfigurable and reprogrammable hardware platform which provide different standards with a common platform, the SDR software framework which control and manage the whole systems, and the protocol processing software modules which is built on reusable protocol libraries. The main idea here is to have a very flexible platform that enables us to test the validity of the following design approaches: FPGA dynamic partial reconfiguration techniques, parameterization design approach using common operators, hierarchical distributed reconfiguration management

Framework for Anomaly Detection in OKL4-Linux Based Smartphones

Smartphones face the same threats as traditional computers. As long as a device has the capabilities to perform logic processing, the threat of running malicious logic exists. The only difference between security threats on traditional computers versus security threats on smartphones is the challenge to understand the inner workings of the operating system on different hardware processor architectures. To improve upon the security of smartphones, anomaly detection capabilities can be implemented at different functional layers of a smartphone in a coherent manner; instead of just looking at individual functional layers. This paper will focus on identifying conceptual points for measuring normalcy in different functional layers of a smartphone based on OKL4 and LiMo Foundation’s platform architecture

Validation platform specification – D5.1

Deliverable D5.1 del projecte Europeu OneFIT (ICT-2009-257385)The present deliverable introduces the OneFIT Proof-of-Concept (PoC) Architecture which will be used as a basis for the validation platform development throughout the project. This PoC Architecture proposal is validated by identifying the roles of the various components in the framework of the OneFIT Scenarios as derived and detailed in WP2. The applied methodology ensures that all required features are appropriately considered. Furthermore, the hardware components available to the project are detailed which are the basis for the development of an integrated validation platform. Their role is highlighted by an instantiation step which maps the PoC Architecture components to the identified hardware components. Finally, a scenario instantiation is derived which illustrates the role of the various hardware components for the validation of selected OneFIT scenarios.Postprint (published version

A Co-Processor Approach for Efficient Java Execution in Embedded Systems

This thesis deals with a hardware accelerated Java virtual machine, named REALJava. The REALJava virtual machine is targeted for resource constrained embedded systems. The goal is to attain increased computational performance with reduced power consumption. While these objectives are often seen as trade-offs, in this context both of them can be attained simultaneously by using dedicated hardware. The target level of the computational performance of the REALJava virtual machine is initially set to be as fast as the currently available full custom ASIC Java processors. As a secondary goal all of the components of the virtual machine are designed so that the resulting system can be scaled to support multiple co-processor cores. The virtual machine is designed using the hardware/software co-design paradigm. The partitioning between the two domains is flexible, allowing customizations to the resulting system, for instance the floating point support can be omitted from the hardware in order to decrease the size of the co-processor core. The communication between the hardware and the software domains is encapsulated into modules. This allows the REALJava virtual machine to be easily integrated into any system, simply by redesigning the communication modules. Besides the virtual machine and the related co-processor architecture, several performance enhancing techniques are presented. These include techniques related to instruction folding, stack handling, method invocation, constant loading and control in time domain. The REALJava virtual machine is prototyped using three different FPGA platforms. The original pipeline structure is modified to suit the FPGA environment. The performance of the resulting Java virtual machine is evaluated against existing Java solutions in the embedded systems field. The results show that the goals are attained, both in terms of computational performance and power consumption. Especially the computational performance is evaluated thoroughly, and the results show that the REALJava is more than twice as fast as the fastest full custom ASIC Java processor. In addition to standard Java virtual machine benchmarks, several new Java applications are designed to both verify the results and broaden the spectrum of the tests.Siirretty Doriast