Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Low Voltage Low Power Analogue Circuits Design

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.

A Study of Voltage-Mode and Current-Mode Filters Using Modified Current Feedback Operational Amplifier

Abstract A Study of Voltage-Mode and Current-Mode Filters Using Modified Current Feedback Operational Amplifier Xin Cui There is a prevalent use of current-mode (CM) circuit techniques in analog integrated circuit design, in view of the fact that CM circuits offer certain advantages over voltage-mode (VM) circuits in terms of certain performance parameters such as propagation delay, dynamic range, and bandwidth. The characteristics of a CM circuit make it not so vulnerable to the current demands of IC design trends, such as continuously decreased size and lower DC supply voltages. Therefore, some active devices that could be exploited in both CM and VM circuits have drawn a lot of attention, such as the second generation current conveyor (CCII) and operational transconductance amplifier (OTA). However, a large amount of effort has been made on VM circuits due to their dominant form of signal processing in analog circuit design for the past several decades. The concept of network transposition, introduced by Bhattacharyya and Swamy as early as in 1971, is a powerful technique to convert a VM circuit to a CM one and vice-versa, with little physical circuit alteration and retaining the same performance as its voltage-mode counterpart. It is especially attractive in transforming those circuits that employ active devices which are transposes of themselves, such as OTA or CCII-. Recently, it has been shown in the literature that a new active element, the modified current feedback operational amplifier (MCFOA), is also its own transpose, and hence can be used to design both VM and CM circuits. It is also known that using the same MCFOA, four equivalent realizations are possible for synthesizing a VM filter function, and further, corresponding four CM filter realizations can be obtained utilizing transposition. However, no detailed study has been conducted with regard to the relative performance of the four equivalent VM structures or the corresponding four CM structures, particularly from the point of view of the non-idealness or the parasitic effects of MCFOA on the performance. This thesis presents a thorough study on band-pass filter (BPF) and notch filter (NF) implemented with MCFOA both in the voltage-mode and their transposed current-mode counterparts. The transfer functions of the four configurations of voltage-mode circuits, as well as that of the current-mode circuits, should be the same when the MCFOA is ideal. However, in practice, they are influenced by parasitic parameters. Accordingly, the performances of the band-pass and notch filters are influenced remarkably by the parasitic parameters of the active device, namely, MCFOA, especially the parasitic resistances for low frequency applications. These effects are studied by comparing the theoretical and SPICE simulation results of the four configurations of the voltage- and current-mode BPF and NF using non-ideal MCFOA. In addition, an improved MCFOA that reduces the effect of parasitic resistances is proposed. Performance of BPF and NF are compared among the four configurations of voltage- and current-mode circuits using the improved MCFOA. They are also compared with those using the original version of MCFOA. It is shown that the proposed MCFOA yields several improvements on the performance of both VM and CM BPFs, such as more attenuation at the low frequencies, and drastic reduction in the ω_p and Q_p errors. Based on the fact that MCFOA is composed of two CCIIs (CCII+ and CCII-), and FTFN can be realized with minor modifications of CCII-, it is natural to compare the performance of BPF using CCII- and FTFN with that using MCFOA. Thus, BPF using CCII- and FTFN and their transposed circuits are also studied. As mentioned earlier, CCII- is its own transpose. However, FTFN does not have a proposed admittance or a hybrid matrix for us to find its transpose. An attempt to find the admittance matrix of FTFN is explored in this thesis. The results show that FTFN can be used as its own transpose only under ideal conditions. Comparisons of performance of BPFs using the original MCFOA, the proposed MCFOA, and CCII-, as well as among their transposes, are presented. It is shown that BPF using the proposed MCFOA exhibits the best performance

High-Linearity Self-Biased CMOS Current Buffer

A highly linear fully self-biased class AB current buffer designed in a standard 0.18 mu m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48 mu W, features an input resistance as low as 89 Omega, high accuracy in the input-output current ratio and total harmonic distortion (THD) figures lower than -60 dB at 30 mu A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications

A quick response four decade logarithmic high-voltage stepping supply

An improved high-voltage stepping supply, for space instrumentation is described where low power consumption and fast settling time between steps are required. The high-voltage stepping supply, utilizing an average power of 750 milliwatts, delivers a pair of mirror images with 64 level logarithmic outputs. It covers a four decade range of + or - 2500 to + or - 0.29 volts having an output stability of + or - 0.5 percent or + or - 20 millivolts for all line load and temperature variations. The supply provides a typical step setting time of 1 millisecond with 100 microseconds for the lower two decades. The versatile design features of the high-voltage stepping supply provides a quick response staircase generator as described or a fixed voltage with the option to change levels as required over large dynamic ranges without circuit modifications. The concept can be implemented up to + or - 5000 volts. With these design features, the high-voltage stepping supply should find numerous applications where charged particle detection, electro-optical systems, and high voltage scientific instruments are used

Robust low power CMOS methodologies for ISFETs instrumentation

I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing

CMOS current amplifiers : speed versus nonlinearity

This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCII∞) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down. In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 μm CMOS-process. These filters use a differential CCII∞ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 μm BiCMOS-process, uses again a CCII∞. This circuit uses a pn-junction as a logarithmic feedback element. With a CCII∞ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 μm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe