Receptores de rádio-frequência melhorados e disruptivos

This Ph.D. mainly addresses the reception part of a radio front end, focusing on Radio Frequency (RF) sampling architectures. These are considered to be the most promising future candidates to get better performance in terms of bandwidth and agility, following the well-known Software-Defined Radio (SDR) concept. The study considers the usage of an RF receiver in a standalone operation, i.e., used for receiving unknown data at the antenna, and when used as observation path for Power Amplifier (PA) linearization via Digital Predistortion (DPD), since nowadays this represents a mandatory technique to increase overall system’s performance. Firstly, commercial available RF Analog-Digital-Converters (ADCs) are studied and characterized to understand their limitations when used in DPD scenarios. A method for characterization and digital post-compensation to improve performance is proposed and evaluated. Secondly, an innovative FPGA-based RF single-bit pulsed converter based on Pulse Width Modulation (PWM) is addressed targeting frequency agility, high analog input bandwidth, and system integration, taking profit of an FPGA-based implementation. The latter was optimized based on PWM theoretical behavior maximizing Signal-to-Noise-Ratio (SNR) and bandwidth. The optimized receiver, was afterwards evaluated in a 5G C-RAN architecture and as a feedback loop for DPD. Finally, a brief study regarding DPD feedback loops in the scope of multiantenna transmitters is presented. This Ph.D. contributes with several advances to the state-of-the-art of SDR receiver, and to the so-called SDR DPD concept.Este doutoramento endereça principalmente a componente de receção de um transcetor de rádio-frequência (RF), focando-se em arquiteturas de receção de amostragem em RF. Estas são assim consideradas como sendo as mais promissoras para o futuro, em termos de desempenho, largura de banda e agilidade, de acordo com o conhecido conceito de Rádios Definidos por Software (SDR). O estudo considera o uso dos recetores de RF em modo standalone, i.e., recebendo dados desconhecidos provenientes da antena, e também quando usados como caminho de observação para aplicação de linearização de amplificadores de potência (PAs) via pré-distorção digital (DPD), pois atualmente esta é uma técnica fundamental para aumentar o desempenho geral do sistema. Em primeiro lugar, os conversores analógico-digital de RF são estudados e caracterizados para perceber as suas limitações quando usados em cenários de DPD. Um método de caracterização e pós compensação digital é proposto para obter melhorias de desempenho. Em segundo lugar, um novo recetor pulsado de um bit baseado em Modulação de Largura de Pulso (PWM) e implementado em Agregado de Células Lógicas Programáveis (FPGA) é endereçado, visando agilidade em frequência, largura de banda analógica e integração de sistema, tirando proveito da implementação em FPGA. Este recetor foi otimizado com base no modelo comportamental teórico da modulação PWM, maximizando a relação sinalruído (SNR) e a largura de banda. O recetor otimizado foi posteriormente avaliado num cenário 5G de uma arquitetura C-RAN e também num cenário em que serve de caminho de observação para DPD. Finalmente, um breve estudo relativo a caminhos de observação de DPD no contexto de transmissores multi-antena é também apresentado. Este doutoramento contribui com vários avanços no estado da arte de recetores SDR e no conceito de SDR DPD.Programa Doutoral em Engenharia Eletrotécnic

Arquiteturas paralelas avançadas para transmissores 5G totalmente digitais

The fifth generation of mobile communications (5G) is being prepared and should be rolled out in the early coming years. Massive number of Radio-Frequency (RF) front-ends, peak data rates of 10 Gbps (everywhere and everytime), latencies lower than 10 msec and huge device densities are some of the expected disruptive capabilities. At the same time, previous generations can not be jeopardized, fostering the design of novel flexible and highly integrated radio transceivers able to support the simultaneous transmission of multi-band and multi-standard signals. The concept of all-digital transmission is being pointed out as a promising architecture to cope with such challenging requirements, due to its fully digital radio datapath. This thesis is focused on the proposal and validation of fully integrated and advanced digital transmitter architectures that excel the state-of-the-art in different figures of merit, such as transmission bandwidth, spectral purity, carrier agility, flexibility, and multi-band capability. The first part of this thesis introduces the concept of all-digital RF transmission. In particular, the foundations inherent to this thematic line are given, together with the recent advances reported in the state-of-the-art architectures.The core of this thesis, containing the main developments achieved during the Ph.D. work, is then presented and discussed. The first key contribution to the state-of-the-art is the use of cascaded Delta-Sigma (∆Σ) architectures to relax the analog filtering requirements of the conventional All-Digital Transmitters while maintaining the constant envelope waveform. Then, it is presented the first reported architecture where Antenna Arrays are directly driven by single-chip and single-bit All-Digital Transmitters, with promising results in terms of simplification of the RF front-ends and overall flexibility. Subsequently, the thesis proposes the first reported RF-stage All-Digital Transmitter that can be embedded within a single Field-Programmable Gate Array (FPGA) device. Thereupon, novel techniques to enable the design of wideband All-Digital Transmitters are reported. Finally, the design of concurrent multi-band transmitters is introduced. In particular, the design of agile and flexible dual and triple bands All-DigitalTransmitter (ADT) is demonstrated, which is a very important topic for scenarios that demand carrier aggregation. This Ph.D. contributes withseveral advances to the state-of-the-art of RF all-digital transmitters.A quinta geração de comunicações móveis (5G) está a ser preparada e deve ser comercializada nos próximos anos. Algumas das caracterı́sticas inovadoras esperadas passam pelo uso de um número massivo de font-ends de Rádio-Frequência (RF), taxas de pico de transmissão de dados de 10 Gbps (em todos os lugares e em todas as ocasiões), latências inferiores a 10 mseg e elevadas densidades de dispositivos. Ao mesmo tempo, as gerações anteriores não podem ser ignoradas, fomentando o design de novos transceptores de rádio flexı́veis e altamente integrados, capazes de suportar a transmissão simultânea de sinais multi-banda e multi-standard. O conceito de transmissão totalmente digital é considerado como um tipo de arquitetura promissora para lidar com esses requisitos desafiantes, devido ao seu datapath de rádio totalmente digital. Esta tese é focada na proposta e validação de arquiteturas de transmissores digitais totalmente integradas e avançadas que ultrapassam o estado da arte em diferentes figuras de mérito, como largura de banda de transmissão, pureza espectral, agilidade de portadora, flexibilidade e capacidade multibanda. A primeira parte desta tese introduz o conceito de transmissores de RF totalmente digitais. Em particular, os fundamentos inerentes a esta linha temática são apresentados, juntamente com os avanços mais recentes do estado-da-arte. O núcleo desta tese, contendo os principais desenvolvimentos alcançados durante o trabalho de doutoramento, é então apresentado e discutido. A primeira contribuição fundamental para o estado da arte é o uso de arquiteturas em cascata com moduladores ∆Σ para relaxar os requisitos de filtragem analógica dos transmissores RF totalmente digitais convencionais, mantendo a forma de onda envolvente constante. Em seguida, é apresentada a primeira arquitetura em que agregados de antenas são excitados diretamente por transmissores digitais de um único bit inseridos num único chip, com resultados promissores em termos de simplificação dos front-ends de RF e flexibilidade em geral. Posteriormente, é proposto o primeiro transmissor totalmente digital RF-stage relatado que pode ser incorporado dentro de um único Agregado de Células Lógicas Programáveis. Novas técnicas para permitir o desenho de transmissores RF totalmente digitais de banda larga são também apresentadas. Finalmente, o desenho de transmissores simultâneos de múltiplas bandas é exposto. Em particular, é demonstrado o desenho de transmissores de duas e três bandas ágeis e flexı́veis, que é um tópico essencial para cenários que exigem agregação de múltiplas bandas.Apoio financeiro da Fundação para a Ciência e Tecnologia (FCT) no âmbito de uma bolsa de doutoramento, ref. PD/BD/105857/2014.Programa Doutoral em Telecomunicaçõe

Envelope and phase delays correction in an EER radio architecture

International audienceThis article deals with synchronization in the Envelope Elimination and Restoration (EER) type of transmitter architecture. To illustrate the performances of such solution, we choose to apply this architecture to a 64 carriers 16QAM modulated OFDM. We first introduce the problematic of the realisation of a highly linear transmitter.We then present the Envelope Elimination and Restoration solution and draw attention to its major weakness: a high sensitivity to desynchronization between the phase and envelope signal paths. To address this issue, we propose an adaptive synchronization algorithm relying on a feedback loop, a LeastMean Square formulation and involving an interpolation step. It enables the correction of delay mismatches and tracking of possible variations. We demonstrate that the quality of the interpolator has a direct impact on Error Vector Magnitude (EVM) value and output spectrum. Implementation details are provided along with an analysis of the behaviour and performances of the method. We present HPADS and Matlab simulation results and then focus on the enhancement of the transmitter performances using the proposed algorithm

Acoustic Transmitters for Underwater Neutrino Telescopes

In this paper acoustic transmitters that were developed for use in underwater neutrino telescopes are presented. Firstly, an acoustic transceiver has been developed as part of the acoustic positioning system of neutrino telescopes. These infrastructures are not completely rigid and require a positioning system in order to monitor the position of the optical sensors which move due to sea currents. To guarantee a reliable and versatile system, the transceiver has the requirements of reduced cost, low power consumption, high pressure withstanding (up to 500 bars), high intensity for emission, low intrinsic noise, arbitrary signals for emission and the capacity of acquiring and processing received signals. Secondly, a compact acoustic transmitter array has been developed for the calibration of acoustic neutrino detection systems. The array is able to mimic the signature of ultra-high-energy neutrino interaction in emission directivity and signal shape. The technique of parametric acoustic sources has been used to achieve the proposed aim. The developed compact array has practical features such as easy manageability and operation. The prototype designs and the results of different tests are described. The techniques applied for these two acoustic systems are so powerful and versatile that may be of interest in other marine applications using acoustic transmitters.Comment: 21 pages, 14 figures,1 tabl

Active Flat Optics Wavefront Manipulation for Imaging, Ranging, and Sensing

The emergence and maturity of integrated photonic platforms over the past decade allowed for reliable integration of a large number of photonic components on a single substrate. This ability to process and control coherent light on a chip is a potential pathway for the realization of novel low-cost systems capable of non-conventional functionalities for optical wavefront engineering. In this thesis, integrated active flat optics architectures for generation, manipulation, and reception of optical wavefronts are investigated. In particular, the application of such systems for imaging, ranging, and sensing are studied and multiple photonic systems including a large scale transmitter, a high-sensitivity receiver, and a high-resolution transceiver are demonstrated. For generation of optical wavefronts, solutions for engineering a radiative optical waveform via emission by an array of nano-photonic antennas are studied and a chip-scale photonic transmitter is implemented. The transmitter forms an optical phased array with a novel architecture in a CMOS compatible silicon photonics process which not only dispenses with the limitations of previously demonstrated systems but also yields a narrower beamwidth leading to a higher resolution. Moreover, an integrated adaptive flat optical receiver architecture that collects samples of the incident light and processes it on-chip with high detection sensitivity is implemented. To detect the optical samples with a high signal to noise ratio, an optoelectronic mixer is proposed and designed that down-converts the optical signals received by each antenna to a radio frequency signal in the electronic domain, provides conversion gain, and rejects interferers. This system allows arbitrary wavefront manipulation of the received signal by adapting itself to new conditions — a capability that does not exist in conventional cameras. Using this system, we realized the first high-sensitivity optical phased array receivers with one-dimensional and two-dimensional apertures and the functionality of the chips as ultra-thin lens-less cameras were demonstrated. To achieve a high-resolution integrated photonic 3D imager with low system complexity, a double spectral sampling method is developed through a special wavefront sampling arrangement on the transmitter and receiver apertures. This transceiver architecture includes a multi-beam transmitter and a high-sensitivity receiver that can distinguish the illuminated points separately and process them simultaneously using a digital signal processor. Moreover, novel ultra-low power architectures for generation and reception of short RF/microwave pulses are explored. Such systems have a broad range of applications including imaging and ranging. In this study, the capability of generating and receiving orthogonal Hermite pulses of various orders using a capacitor-only time-varying network is demonstrated.</p

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Design of an Autonomous Hovering Miniature Air Vehicle as a Flying Research Platform

This thesis, by developing a Miniature Aerial Vehicle (MAV) hovering platform, presents a practical solution to allow researchers and students to implement their theoretical methods for guidance and navigation in the real world. The thesis is not concerned with the development of guidance and navigation algorithms, nor is it concerned with the development of external sensors. There have been some recent advances in guidance and navigation towards developing algorithms and simple sensors for MAVs. The task of developing a platform to test such advancements is the subject of this thesis. It is considered a difficult and time consuming process due to the complexities of autonomous flight control and the strict size, weight and computational requirements of this type of system. It would be highly beneficial to be able to buy a platform specifically designed for this task that already possesses autonomous hovering capability and the expansion connectivity for interfacing your own custom developed sensors and algorithms. Many biological and computer scientists would jump at the opportunity to maximize their research by real world implementation. The development of such a system is not a trivial task. It requires a great deal of understanding in a broad range of fields including; Aeronautical, Microelectronic, Mechanical, Computer and Embedded Software Engineering in order to create a successful prototype. The challenge of this thesis was to design a research platform to enable easy implementation of external sensors and guidance algorithms, in a real world environment for research and education. The system is designed so it could be used for a broad range of testing experiments. After extensive research in current MAV and avionics design it became obvious in several areas the best available products were not sufficient to meet the needs of the proposed platform. Therefore it was necessary to custom design and build; sensors, a data acquisition system and a servo controller. The latter two products are available for sale by Jimonics (www.jimonics.com). It was then necessary to develop a complete flight control system with integrated sensors, processor and wireless communications network which is called ‘The MicroBrain’. ‘The MicroBrain’ board measures only 45mm x 35mm x 11mm and weighs ~11 grams. The coaxial contra-rotating MAV platform design provides a high level of mechanical stability to help minimise the control system complexity. The platform was highly modified from a commercially available remotely controlled helicopter. The system incorporates a novel collision protection system that was designed to also double as a mounting place for external sensors around its perimeter. The platform equipped with ‘The MicroBrain’ is capable of fully autonomous hover. This provides a great base for testing guidance and navigational sensors and algorithms by decoupling the difficult task of platform design and low-level stability control. By developing a platform with these capabilities the researcher can now focus on the guidance and navigation task, as the difficulties in developing a custom platform have been taken care of. This therefore promotes a faster evolution of guidance and navigational control algorithms for MAVs

Digital Radio Encoding and Power Amplifier Design for Multimode and Multiband Wireless Communications

The evolution of wireless technology has necessitated the support of multiple communication standards by mobile devices. At present, multiple chipsets/radios operating at predefined sets of modulation schemes, frequency bands, bandwidths and output power levels are used to achieve this objective. This leads to higher component counts, increased cost and limits the capacity to cope with future communication standards. In order to tackle different wireless standards using a single chipset, digital circuits have been increasingly deployed in radios and demonstrated re-configurability in different modulation schemes (multimode) and frequency bands (multiband). Despite efforts and progress made in digitizing the entire radio, the power amplifier (PA) is still designed using an conventional approach and has become the bottleneck in digital transmitters, in terms of low average power efficiency, poor compatibility with modern CMOS technology and limited re-configurability. This research addresses these issues from two aspects. The first half of the thesis investigates signal encoding issues between the modulator and PA. We propose, analyze and evaluate a new hybrid amplitude/time signal encoding scheme that significantly improves the coding efficiency and dynamic range of a digitally modulated power amplifier (DMPA) without significantly increasing design complexity. The proposed hybrid amplitude/time encoding scheme combines both the amplitude domain and the time domain to optimally encode information. Experimental results show that hybrid amplitude/time encoding results in a 35% increase in the average coding efficiency with respect to conventional time encoding, and is only 6.7% lower than peak efficiency when applied to a Wireless Local Area Network (WLAN) signal with a peak to average power ratio equal to 9.9 dB. A new DMPA architecture, based on the proposed hybrid encoding, is also proposed. The second half of this thesis presents the design, analysis and implementation of a CMOS PA that is amenable to the proposed hybrid encoding scheme. A multi-way current mode class-D PA architecture has been proposed and realized in 130 nm CMOS technology. The designed PA has satisfied the objectives of wide bandwidth (1.5 GHz - 2.7 GHz at 1 dB output power), and high efficiency (PAE 63%) in addition to demonstrating linear responses using the proposed digital encoding. A complete digital transmitter combining the encoder and the multi-way PA was also investigated. The overall efficiency is 27% modulating 7.3 dB peak to average power ratio QAM signals

HMOS: Head Control Mouse Person with Disability

This paper presents an idea to build a human machine interface for disable persons. The purposed idea is very economical and useful for those disable persons who cannot use their hands to control computers.The main focus is to control the mouse through their head movements by using head-tilt sensor and air blow sensor. The system uses dual axis accelerometer based tilt sensor for detecting the movement of the head which is mounted on the headset and clicking of the mouse is activated by the 2 air blow sensor which are placed near the mouth to detect the left and right click of the mouse from the effect of the air blow in to the sensors. Since the device relies only on the user?s head and air blow, so it can be used easily without requiring too much energy neither in the head movement nor in the air blow for clicking. This system encourage the disable person to start their independent professional life

Synchronous meteorological satellite system description document, volume 3

The structural design, analysis, and mechanical integration of the synchronous meteorological satellite system are presented. The subjects discussed are: (1) spacecraft configuration, (2) structural design, (3) static load tests, (4) fixed base sinusoidal vibration survey, (5) flight configuration sinusoidal vibration tests, (6) spacecraft acoustic test, and (7) separation and shock test. Descriptions of the auxiliary propulsion subsystem, the apogee boost motor, communications system, and thermal control subsystem are included