Wide Frequency Range Superheterodyne Receiver Design and Simulation

The receiver is the backbone of modern communication devices. The primary purpose of a reliable receiver is to recover the desired signal from a wide spectrum of transmitted sources. A general radio receiver usually consists of two parts, the radio frequency (RF) front-end and the demodulator. RF front-end receiver is roughly defined as the entire segment until the analog-to-digital converter (ADC) placed before digital demodulation. Theoretically, a radio receiver must be able to accommodate several tradeoffs such as spectral efficiency, low noise figure (NF), low power consumption, and high power gain. The superheterodyne receiver consisting of double downconversion can well balance the tradeoffs required for the receiver design. In this thesis, the RF front-end superheterodyne receiver design and implementation is presented. Instead of fixed radio frequency of system-on-chip (SOC) design which has been a popular research topic, a radio receiver operating in the wide frequency range of roughly 2.53 GHz to 2.83 GHz located in IEEE S-band is considered. The wide frequency range receiver is suitable for applications like Direct-to-Home satellite television systems, which allocates from 2.5 GHz to 2.7 GHz. This thesis is focusing on the off-chip receiver design for the objectives of processing a wider frequency band while providing high linearity and power gain. The important active devices in a receiver which are low noise amplifiers (LNA), power amplifiers (PA), and mixers are designed and implemented. In this work, the two-stage LNA designed provides low NF and good input standing wave ratio (VSWR). The class-A PA is designed utilizing the load-pull method for maximum power transfer and highest possible power added efficiency (PAE). The mixer design adopts the double balance fully differentially (Gilbert) topology which is ideal for low port feedthrough, intermodulation distortion, and moderate conversion gain. The self-built active devices (e.g. amplifiers and mixers) and band-pass filters (BPF) provided by Agilent EEsof Advance System Design (ADS) are combined into a double downconversion RF front-end receiver. The receiver sensitivity and selectivity is assessed and tabulated. Also, the operation in the wide frequency range of roughly 2.53 GHz to 2.83 GHz with the last intermediate frequency (IF) of 20 MHz is verified

Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters

A general framework for performance optimization of continuous-time OTA-C (Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary order are developed based on the matrix description of a general OTA-C filter model . Since these procedures use OTA macromodels, they can be used to obtain the results significantly faster than transistor-level simulation. In the case of transient analysis, the speed-up may be as much as three orders of magnitude without almost no loss of accuracy. This makes it possible to carry out direct numerical optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. The above features are a basis to build automated optimization procedures for OTA-C filters. In particular, a systematic optimization procedure using equivalence transformations is proposed. The research also proposes suitable software implementations of the optimization process. The first part of the research proposes a general performance optimization procedure and to verify the process two application type examples are mentioned. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in standard 0.5mm CMOS process. The second part of the research proposes a new linearization technique to improve the linearity of an OTA using an Active Error Feedforward technique. Most present day applications require very high linear circuits combined with low noise and low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm CMOS process. The measurement results for the filter and the stand alone OTA have been discussed. The research focuses on these issues