Concepts and methods in optimization of integrated LC VCOs

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-μm MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

Distributed Integrated Circuits: An Alternative Approach to High-Frequency Design

Distributed integrated circuits are presented as a methodology to design high-frequency communication building blocks. Distributed circuits operate based on multiple parallel signal paths working in synchronization that can be used to enhance the frequency of operation, combine power, and enhance the robustness of the design. These multiple signal paths usually result in strong couplings inside the circuit that necessitate a treatment spanning architecture, circuits, devices, and electromagnetic levels of abstraction

The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology

This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS

Lossy/Lossless Floating/Grounded Inductance Simulation Using One DDCC

In this work, we present new topologies for realizing one lossless grounded inductor and two floating, one lossless and one lossy, inductors employing a single differential difference current conveyor (DDCC) and a minimum number of passive components, two resistors, and one grounded capacitor. The floating inductors are based on ordinary dual-output differential difference current conveyor (DO-DDCC) while the grounded lossless inductor is based one a modified dual-output differential difference current conveyor (MDO-DDCC). The proposed lossless floating inductor is obtained from the lossy one by employing a negative impedance converter (NIC). The non-ideality effects of the active element on the simulated inductors are investigated. To demonstrate the performance of the proposed grounded inductance simulator as an example, it is used to construct a parallel resonant circuit. SPICE simulation results are given to confirm the theoretical analysis

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

Design issues in CMOS differential LC oscillators

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors

A Noise-Shifting Differential Colpitts VCO

A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples

Methods and tools for the design of RFICs

Ambient intelligence is going to focus the next advances in wireless technologies. Hence, the increasing demand on radio frequency (RF) devices and applications represents, not only a challenge for technological industries to improve its roadmaps, but also for RF engineers to design more robust, low-power, small-size and low-cost devices. Regarding to communication robustness, in the latest years, differential topologies have acquired an important relevance because of its natural noise and interference immunity. Within this framework, a differential n-port device can still be treated with the classical analysis circuit theory by means of Z-,Y-, h-parameters or the most suitable S-parameters in the radio frequency field. Despite of it, Bockelman introduced the mixed-mode scattering parameters, which more properly express the differential and common-mode behavior of symmetrical devices. Since then, such parameters have been used with a varying degree of success, as it will be shown, mainly because of a misinterpretation. Thereby, this thesis is devoted to extend the theory of mixed-mode scattering parameters and proposes the methodology to analyze such devices. For this proposal, the simplest case of a two-port device is developed. By solving this simple case, most of the lacks of the current theory are filled up. As instance, it allows the characterization and comparison of symmetric and spiral inductors, which have remained a controversy point until now. After solving this case, the theory is extended to a n-port device. Another key point on the fast and inexpensive development of radio frequency devices is the advance on fast CAD tools for the analysis and synthesis of passive devices. In the case of silicon technologies, planar inductors have become the most popular shapes because of its integrability. However, the design of inductors entails a deep experience and acknowledge not only on the behavior of such devices but on the use of electromagnetic (EM) simulators. Unfortunately, the use of EM simulators consumes an important quantity of time and resources. Thereby, this thesis is devoted to improve some of the aspects that slow down the synthesis process of inductors. Therefore, an ‘ab initio’ technique for the meshing of planar radio frequency and microwave circuits is described. The technique presented can evaluate the losses in the component with a high accuracy just in few seconds where an electromagnetic simulator would normally last hours. Likewise, a simple bisection algorithm for the synthesis of compact planar inductors is presented. It is based on a set of heuristic rules obtained from the study of the electromagnetic behavior of these planar devices. Additionally, design of a single-ended to differential low noise amplifier (LNA) in a CMOS technology is performed by using the methods and tools described.L'enginyeria de radiofreqüència i la tecnologia de microones han assolit un desenvolupament inimaginable i avui en dia formen part de la majoria de les nostres activitats diàries. Probablement, la tecnologia mòbil ha tingut un desenvolupament més ràpid que qualsevol altre avenç tecnològic de l'era digital. Avui en dia, podem dir que el paradigma de la mobilitat s'ha assolit i tenim accés ràpid a internet des de qualsevol lloc on podem estar amb un dispositiu de butxaca. No obstant això, encara hi ha fites per endavant. Es més que probable que el paradigma de l’ "ambient intelligence” sigui el centre dels pròxims avenços en les tecnologies sense fils. A diferencia del paradigma de l"ambient intelligence', l'evolució de la tecnologia de la informació mai ha tingut l'objectiu explícit de canviar la societat, sinó que ho van fer com un efecte secundari, en canvi, les visions d' “ambient intelligence” proposen expressament el transformar la societat mitjançant la connexió completa i la seva informatització. Per tant, l'augment de la demanda de dispositius de ràdio freqüència (RF) i de les seves possibles aplicacions representa, no només un repte per a les indústries tecnològiques per millorar els seus plans de treball, sinó també per als enginyers de RF que hauran de dissenyar dispositius de baixa potència, més robusts, de mida petita i de baix cost. Quant a la robustesa dels dispositius, en els últims anys, les topologies de tipus diferencial han adquirit una important rellevància per la seva immunitat natural al soroll i resistència a les interferències. Dins d'aquest marc, un dispositiu de nports diferencial, encara pot ser tractat com un dispositiu 2nx2n i la teoria clàssica d'anàlisi de circuits (és a dir, la temia de quadripols) es pot aplicar a través de paràmetres Z, Y, h o els paràmetres S, més adequats en el camp de freqüència de ràdio. Tot i això, Bockelman i Eisenstadt introdueixen els paràmetres S mixtos, que expressen més adequadament el comportament diferencial i en mode comú de dispositius simètrics o asimètrics. Des de llavors, aquests paràmetres s'han utilitzat amb un grau variable d'èxit, com es mostrarà, principalment a causa d'una mala interpretació. D'aquesta manera, la primera part d'aquesta tesi està dedicada a estendre la teoria dels paràmetres S de mode mixt i proposa la metodologia d'anàlisi d'aquest tipus de dispositius i circuits. D'aquesta forma, en el Capítol 2, es desenvolupa el cas més simple d'un dispositiu de dos ports. En resoldre aquest cas simple, la major part de les mancances de la teoria actual es posen de relleu. Com a exemple, pennet la caracterització i la comparació de bobines simètriques i espiral no simètriques, que han estat un punt de controvèrsia fins ara. Després de resoldre aquest cas, al Capítol 3 s'estén la teOIia a un dispositiu de n-ports dels quals un nombre pot ser single-ended i la resta diferencials. És en aquest moment quan la dualitat existent entre els paràmetres S estàndard i de mode mixt es pot veure clarament i es destaca en el seu conjunt. Aquesta teoria permet, tanmateix, estendre la teoria clàssica d'amplificadors quan s'analitzen per mitjà de paràmetres S. Un altre punt clau en el desenvolupament ràpid i de baix cost dels dispositius de radiofreqüència és l'avenç en les eines CAD ràpides per a l'anàlisi i síntesi dels dispositius passius, en especial dels inductors. Aquests dispositius apareixen tot sovint en el disseny de radio freqüència degut a la seva gran versatilitat. Tot i que hi ha hagut múltiples intents de reemplaçar amb components externs o circuits, fins i tot actius, en el cas de les tecnologies de silici, els inductors planars s'han convertit en les formes més populars per la seva integrabilitat. No obstant això, el disseny d'inductors implica conèixer i posseir una experiència profunda no només en el comportament d'aquests dispositius, però també en l'ús de simuladors electromagnètics (EM). Desafortunadament, l'ús dels simuladors EM consumeix una quantitat important de temps i recursos. Per tant, la síntesi dels inductors representa un important inconvenient actualment. D'aquesta manera, la segona part d'aquesta tesi està dedicada a millorar alguns dels aspectes que frenen el procés de síntesi dels inductors. Per tant, en el Capítol 4, es descriu una tècnica 'ab initio' de generació de la malla per bobines planars en ràdio freqüència i microones. La tècnica es basa en l'estudi analític dels fenòmens d'aglomeració de corrent que tenen lloc a l'interior del component. En aquesta avaluació, no es requereix una solució explícita dels corrents i de les càrregues arreu del circuit. Llavors, el nombre de cel•les de la malla assignades a una tira de metall donada, depèn del valor inicialment obtingut a partir de l'estudi analític. La tècnica presentada pot avaluar les pèrdues en el component amb una gran precisió només en uns pocs segons, quan comparat amb un simulador electromagnètic normalment es necessitaria hores. De la mateixa manera, en el Capítol 5 es presenta un senzill algoritme de bisecció per a la síntesi d'inductors planars compactes. Es basa en un conjunt de regles heurístiques obtingut a partir de l'estudi del comportament electromagnètic d'aquests dispositius planars. D'aquesta manera, el nombre d'iteracions es manté moderadament baix.D'altra banda, per tal d'accelerar l'anàlisi en cada pas, s'utilitza un simulador ràpid electromagnètic planar, el qual es basa en el coneixement que es té del component sintetitzat. Finalment, en el Capítol 6, la metodologia de paràmetres S de mode mixt proposada i les eines CAD introduides s'utilitzen àmpliament en el disseny d'un amplificador de baix soroll “single-ended” a diferencial (LNA), mitjançant una tecnologia estàndard CMOS.L'amplificador de baix soroll és un dels components claus en un sistema de recepció de radio freqüència, ja que tendeix a dominar la sensibilitat i la figura de soroll (NF) de tot el sistema. D'altra banda, les característiques d'aquest circuit estan directament relacionades amb els components actius i passius disponibles en una tecnologia donada. Per tant, la tecnologia escollida, el factor de qualitat dels passius, i la forma com es caracteritzen tindran un alt impacte en les principals figures de mèrit del circuit real

Low-power transceiver design for mobile wireless chemical biological sensors

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode