FPGA를 이용한 시간 기반 고집적 PET 데이터 수집 장치

학위논문(박사)--서울대학교 대학원 :의과대학 의과학과,2019. 8. 이재성.Positron emission tomography (PET) is a widely used functional imaging device for diagnosing cancer and neurodegenerative diseases. PET instrumentation studies focus on improving both spatial resolution and sensitivity to improve the lesion detectability while reducing radiation exposure to patients. The silicon photomultiplier (SiPM) is a photosensor suitable for high-performance PET scanners owing to its compact size and fast response. However, the SiPM-based PET scanners require a large number of readout channels owing to a high level of granularity. For example, the typical whole-body PET scanners require more than 40,000 SiPM channels. Therefore, the highly integrated data acquisition (DAQ) system that can digitize a large number of SiPM signal with preserving its fast temporal response is required to develop the high-performance SiPM-based PET scanners. Time-based signal digitization is a promising method to develop highly integrated DAQ systems owing to its simple circuitry and fast temporal response. In this thesis, studies on developing highly integrated DAQ systems using a field-programmable gate array (FPGA) were presented. Firstly, a 10-ps time-to-digital converter (TDC) implemented within the FPGA was developed. The FPGA-TDCs suffer from the non-linearity, because FPGAs are not originally designed to implement TDC. We proposed the dual-phase sampling architecture considering the FPGA clock distribution network to mitigate the TDC non-linearity. In addition, we developed the on-the-fly calibrator that compensated the innate bin width variations without introducing the dead time. Secondly, the time-based SiPM multiplexing and readout method was developed using the principle of the global positioning system (GPS). The signal traces connecting every SiPM to four timing channels were used to encode the position information. The position information was obtained using the innate transit time differences measured by four FPGA-TDCs. In addition, the minimal signal distortion by multiplexing circuit allowed to use a time-over-threshold (ToT) method for energy measurement after multiplexing. Thirdly, we proposed a new FPGA-only digitizer. The programmable FPGA input/output (I/O) port was configured with stub-series terminated logic (SSTL) input receiver, and each FPGA I/O port functioned as a high-performance voltage comparator with a fast temporal response. We demonstrated that the FPGA can be used as a high-performance DAQ system by directly digitizing the time-of-flight (TOF) PET detector signals using the FPGA without any front-end electronics. Lastly, we developed comparator-less charge-to-time converter (QTC) DAQ systems to collect data from a prototype high-resolution brain PET scanner. The energy channel consisted of a QTC combined with the SSTL input receiver of the FPGA. The timing channel was a TDC implemented within the same FPGA. The detailed structure of brain phantom was well-resolved using the developed high-resolution brain PET scanner and the highly-integrated time-based DAQ systems.양전자방출단층촬영 (Positron Emission Tomography; PET) 장치는 암과 신경퇴행성 질환을 영상화하는 데 널리 쓰이는 기능 영상장치이다. 최근 PET 스캐너 연구는 공간 분해능과 장비 민감도를 높여 병변의 진단을 쉽게 하면서 환자의 방사선 피폭을 줄이는 방법에 초점을 맞추고 있다. 실리콘 관증배기 (silicon photomultiplier; SiPM)은 크기가 작고 반응속도가 빠르기 때문에 고성능 PET 스캐너에 적합한 광검출소자이다. 하지만 SiPM 기반 PET 스캐너는 개별 SiPM의 크기가 작기 때문에 수많은 데이터 수집 채널이 필요하다. 예를 들어, 전신 PET 스캐너를 SiPM으로 구성할 경우 40,000개 이상의 SiPM 소자가 필요하다. 따라서, SiPM의 성능을 유지하면서 다채널 신호 디지털화가 가능한 고집적 데이터 수집장치 (data acquisition; DAQ)가 고성능 SiPM PET 스캐너 개발에 필요하다. 시간 기반 신호 디지털 방법은 단순한 회로와 빠른 반응속도 덕분에 고집적 DAQ 시스템을 구현하는 유망한 방법이다. 본 학위논문에서는 프로그램 가능 게이트 배열 (field-programmable gate array; FPGA)을 이용하여 고집적 DAQ 시스템을 개발하는 연구내용을 다룬다. 첫째로, 10 ps 의 분해능을 갖는 FPGA 기반 시간-디지털 변환기 (time-to-digital converter; TDC)를 개발하였다. FPGA는 TDC 구현을 위한 집적소자가 아니므로 FPGA에 구현된 TDC는 일반적으로 비선형성 문제를 가진다. 이를 해결하기 위해 비선형성 문제를 야기하는 FPGA의 클락 신호 분배 구조를 고려하여 이중 위상 샘플링 방법을 제안하였다. 또한, FPGA TDC 고유의 불균일한 분해능을 측정하고 보상하기 위하여 실시간 보정기술을 개발하였다. 둘째로, GPS 원리를 사용한 시간 기반 신호 부호화 (multiplexing) 및 수집 방법을 개발하였다. 부호화 회로는 SiPM을 네 개의 시간 수집 채널로 연결한 도선으로 구성되고 위치정보는 각 SiPM으로부터 네 개의 시간 수집 채널까지의 고유한 도파시간 차이를 계산해서 수집할 수 있다. 또한, 기존 전하 분배 부호화 회로와 달리 신호가 왜곡되지 않기 때문에 문턱 전압 방법 (time-over-threshold; ToT) 방식으로 에너지를 수집하는 것이 가능하였다. 셋째로, FPGA만으로 아날로그 신호를 디지털화 하는 새로운 방법을 개발하였다. FPGA의 프로그램 가능 입출력포트를 stub-series terminated logic (SSTL) 수신기로 프로그램하면, 각각의 FPGA 입출력포트가 빠른 시간 반응성을 가진 고성능 전압비교기로 동작한다. 비정시간 (time-of-flight; TOF) 측정 가능 PET 검출기의 신호를 전단회로 없이 FPGA만으로 디지털화하여 FPGA를 고성능 DAQ 장치로 사용할 수 있음을 입증하였다. 마지막으로, 공간분해능이 뛰어난 뇌전용 스캐너로부터 데이터를 수집하기 위해 전압비교기를 사용하지 않는 시간 기반 DAQ 장치를 개발하였다. 에너지 측정 채널은 시간-전하 변환기 (charge-to-time converter; QTC)와 FPGA의 SSTL 수신기로 구성하였다. 시각 측정 채널은 FPGA 기반 TDC로 구성하였다. 개발한 뇌전용 스캐너와 고집적 시간 기반 DAQ 장치로 획득한 뇌모양 팬텀의 자세한 구조들은 잘 구분되었다.Chapter 1. Introduction 1 1.1. Background 1 1.1.1. Positron Emission Tomography 1 1.1.2. Silicon Photomultiplier 1 1.1.3. Data Acquisition System 2 1.1.4. Time-based Signal Digitization Method 3 1.2. Purpose of Research 6 Chapter 2. FPGA-based Time-to-Digital Converter 8 2.1. Background 8 2.2. Materials and Methods 9 2.2.1. Tapped-Delay-Line TDC 9 2.2.2. FPGA 11 2.2.3. Dual-Phase TDL TDC with On-the-Fly Calibrator 11 2.2.3.1. FPGA Clock Distribution Network 11 2.2.3.2. The Principle of Dual-Phase TDL TDC 14 2.2.3.3. The Principle of Pipelined On-the-Fly Calibrator 16 2.2.3.4. Implementation of Dual-Phase TDL TDC with On-the-Fly Calibrator 18 2.2.4. Experimental Setups and Data Processing 20 2.2.4.1. TDC Characteristics 21 2.2.4.2. Arrival Time Difference Measurements 22 2.3. Results 24 2.3.1. TDC Characteristics 24 2.3.2. Arrival Time Difference Measurements 25 2.4. Discussion 28 Chapter 3. Time-based Multiplexing Method 29 3.1. Background 29 3.2. Materials and Methods 30 3.2.1. Delay Grid Multiplexing 30 3.2.2. Detector for Concept Verification 32 3.2.3. Front-end Electronics 34 3.2.4. Experimental Setups 35 3.2.4.1. Data Acquisition Using the Waveform Digitizer 37 3.2.4.2. Data Acquisition Using the FPGA-TDC 37 3.2.5. Data Processing and Analysis 38 3.2.5.1. Waveform Digitizer 38 3.2.5.2. FPGA-TDC 41 3.3. Results 44 3.3.1. Waveform Digitizer 44 3.3.1.1. Waveform, Rise Time, and Decay Time 44 3.3.1.2. Flood Map 46 3.3.1.3. Energy 48 3.3.1.4. CTR 49 3.3.2. FPGA-TDC 50 3.3.2.1. ToT and Energy 50 3.3.2.2. Flood Map 51 3.3.2.3. CTR 52 3.4. Discussion 53 Chapter 4. FPGA-Only Signal Digitization Method 54 4.1. Background 54 4.2. Materials and Methods 56 4.2.1. Single-ended Memory Interface Input Receiver 56 4.2.2. SeMI Digitizer 56 4.2.3. Experimental Setup for Intrinsic Performance Characterization 59 4.2.3.1. ToT 59 4.2.3.2. Timing 60 4.2.4. Experimental Setup for Individual Signal Digitization 60 4.2.4.1. TOF PET Detector 60 4.2.4.2. Data Acquisition Using the Waveform Digitizer 61 4.2.4.3. Data Acquisition Using the SeMI Digitizer 63 4.2.4.4. Data Analysis 63 4.3. Results 64 4.3.1. Results of Intrinsic Performance Characterization 64 4.3.1.1. ToT 64 4.3.1.2. Timing 65 4.3.2. Results of Individual Signal Digitization 66 4.3.2.1. Energy 66 4.3.2.2. CTR 67 4.4. Discussion 68 Chapter 5. Comparator-less QTC DAQ Systems for High-Resolution Brain PET Scanners 70 5.1. Background 70 5.2. Materials and Methods 72 5.2.1. Brain PET Scanner 72 5.2.1.1. Block Detector 72 5.2.1.2. Sector 73 5.2.1.3. Scanner Geometry 74 5.2.2. Comparator-less QTC DAQ System 75 5.2.3. Data Acquisition Chain of Brain PET Scanner 79 5.2.4. Experimental Setups and Data Processing 79 5.2.4.1. Energy Linearity 79 5.2.4.2. Performance Evaluation of Block Detector 80 5.2.4.3. Phantom Studies 82 5.3. Results 83 5.3.1. Energy Linearity 83 5.3.2. Performance Evaluation of Block Detector 83 5.3.3. Phantom Studies 85 5.4. Discussion 87 Chapter 6. Conclusions 89 Bibliography 90 Abstract in Korean (국문 초록) 94Docto

Power efficient, event driven data acquisition and processing using asynchronous techniques

PhD ThesisData acquisition systems used in remote environmental monitoring equipment and biological sensor nodes rely on limited energy supply soured from either energy harvesters or battery to perform their functions. Among the building blocks of these systems are power hungry Analogue to Digital Converters and Digital Signal Processors which acquire and process samples at predetermined rates regardless of the monitored signal’s behavior. In this work we investigate power efficient event driven data acquisition and processing techniques by implementing an asynchronous ADC and an event driven power gated Finite Impulse Response (FIR) filter. We present an event driven single slope ADC capable of generating asynchronous digital samples based on the input signal’s rate of change. It utilizes a rate of change detection circuit known as the slope detector to determine at what point the input signal is to be sampled. After a sample has been obtained it’s absolute voltage value is time encoded and passed on to a Time to Digital Converter (TDC) as part of a pulse stream. The resulting digital samples generated by the TDC are produced at a rate that exhibits the same rate of change profile as that of the input signal. The ADC is realized in 0.35mm CMOS process, covers a silicon area of 340mm by 218mm and consumes power based on the input signal’s frequency. The samples from the ADC are asynchronous in nature and exhibit random time periods between adjacent samples. In order to process such asynchronous samples we present a FIR filter that is able to successfully operate on the samples and produce the desired result. The filter also poses the ability to turn itself off in-between samples that have longer sample periods in effect saving power in the process

Voltage-to-Time Converter for High-Speed Time-Based Analog-to-Digital Converters

In modern complementary metal oxide semiconductor (CMOS) technologies, the supply voltage scales faster than the threshold voltage (Vth) of the transistors in successive smaller nodes. Moreover, the intrinsic gain of the transistors diminishes as well. Consequently, these issues increase the difficulty of designing higher speed and larger resolution analog-to-digital converters (ADCs) employing voltage-domain ADC architectures. Nevertheless, smaller transistor dimensions in state-of-the-art CMOS technologies leads to reduced capacitance, resulting in lower gate delays. Therefore, it becomes beneficial to first convert an input voltage to a 'time signal' using a voltage-to-time converter (VTC), instead of directly converting it into a digital output. This 'time-signal' could then be converted to a digital output through a time-to-digital converter (TDC) for complete analog-to-digital conversion. However, the overall performance of such an ADC will still be limited to the performance level of the voltage-to-time conversion process. Hence, this thesis presents the design of a linear VTC for a high-speed time-based ADC in 28 nm CMOS process. The proposed VTC consists of a sample-and-hold (S/H) circuit, a ramp generator and a comparator to perform the conversion of the input signal from the voltage to the time domain. Larger linearity is attained by integrating a constant current (with high output impedance) over a capacitor, generating a linear ramp. The VTC operates at 256 MSPS consuming 1.3 mW from 1 V supply with a full-scale 1 V pk-pk differential input signal, while achieving a time-domain output signal with a spurious-free-dynamic-range (SFDR) of 77 dB and a signal-to-noise-and-distortion ratio (SNDR) of 56 dB at close to Nyquist frequency (f = 126.5 MHz). The proposed VTC attains an output range of 2.7 ns, which is the highest linear output range for a VTC at this speed, published to date

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

A highly digital microbolometer ROIC employing a novel event-based readout and two-step time to digital converters

Uncooled infrared imaging systems are a light weight and low cost alternative to their cooled counterparts. Uncooled microbolometer IR focal plane arrays (IRFPAs) for applications such as medical imaging, thermography, night vision, surveillance and industrial process control have recently been under focus. These systems have small pixel pitches ( 250 K). Low NETD demands excellent microbolometer and readout noise performance. If sensitive analog circuits, driving long metal interconnects, are part of the predigitization readout channel, this necessitates the use of power consuming buffers, potentially in conjunction with noise cancellation circuits that result in power and area overhead. Thus re-thinking at the architectural level is crucial to meet these demands. Accordingly, in this thesis a column-parallel readout architecture for frame synchronous microbolometer imagers is proposed that enables low power operation by employing a time mode digitizer. The proposed readout circuit is based on a bridge type detector network with active and reference microbolometers and employs a capacitive transimpedance amplifier (CTIA) incorporating a novel two-step integration mechanism. By using a modified reset scheme in the CTIA, a forward ramp is initiated at the input side followed by the conventional backward integrated ramp at the output. This extends the measurement interval and improves signal-to-noise ratio (SNR). A synchronous counter based TDC measures this interval providing robust digitization. This technique also provides a way of compensating for self-heating effects. Being highly digital, the proposed architecture offers robust frontend processing and achieves a per channel power consumption of 66 µW, which is considerably lower than the most recently reported designs, while maintaining better than 10mK readout NETD

Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 175-181).Advanced CMOS processes offer very fast switching speed and high transistor density that can be utilized to implement analog signal processing functions in interesting and unconventional ways, for example by leveraging time as a signal domain. In this context, voltage controlled ring oscillators are circuit elements that are not only very attractive due to their highly digital implementation which takes advantage of scaling, but also due to their ability to amplify or integrate conventional voltage signals into the time domain. In this work, we take advantage of voltage controlled oscillators to implement analog- and time-to-digital converters with first-order quantization and mismatch noise-shaping. To implement a time-to-digital converter (TDC) with noise-shaping, we present a oscillator that is enabled during the measurement of an input, and then disabled in between measurements. By holding the state of the oscillator in between samples, the quantization error is saved and transferred to the following sample, which can be seen as first-order noise-shaping in the frequency domain. In order to achieve good noise shaping performance, we also present key details of a multi-path oscillator topology that is able to reduce the effective delay per stage by a factor of 5 and accurately preserve the quantization error from measurement to measurement. An 11-bit, 50Msps prototype time-to-digital converter (TDC) using a multi-path gated ring oscillator with 6ps of delay per stage demonstrates over 20dB of ist-order noise shaping. At frequencies below 1MHz, the TDC error integrates to 80fsrms for a dynamic range of 95dB with no calibration of differential non-linearity required. The 157x258pm TDC is realized in 0.13ipm CMOS and operates from a 1.5V supply.(cont.) The use of VCO-based quantization within continuous-time (CT) [Epsilon] [Delta] ADC structures is also explored, with a custom prototype in 0.13pm CMOS showing measured performance of 86/72dB SNR/SNDR with 10MHz bandwidth while consuming 40mW from a 1.2V supply and occupying an active area of 640pm X 660pm. A key element of the ADC structure is a 5-bit VCO-based quantizer clocked at 950 MHz which we show achieves first-order noise-shaping of its quantization noise. The quantizer structure allows the second order CT Epsilon] [Delta] ADC topology to achieve third order noise shaping, and direct connection of the VCO-based quantizer to the internal DACs of the ADC provides intrinsic dynamic element matching (DEM) of the DAC elements.by Matthew A. Z. Straayer.Ph.D

Time-based noise-shaping techniques for time-to-digital and analog-to-digital converters

In this dissertation, time-based signal processing techniques and their applications in oversampling and noise-shaping data converters are examined. These techniques demonstrate the ability to shift the burden of high performance analog circuits from the compressed voltage-domain to the augmented time-domain. First, the potential of high order noise-shaping and phase-domain feedback in time-to-digital converters (TDCs) is explored. A prototype phase reference, second-order continuous-time delta-sigma TDC for sensor applications was fabricated in 90nm CMOS and achieves 64 dB dynamic range in 1MHz signal bandwidth. Second, an ultra-high performance oscillator-based delta-sigma modulator architecture is investigated. The proposed circuit is a third-order continuous-time PLL-Based Delta-Sigma Modulator with simulated 77 dB SNDR in 40MHz signal bandwidth with OSR of 16, and is fabricated in 65nm CMOS