Power-constrained Test Scheduling for SoCs under a “no session” scheme

11th International Conference on Very Large Scale Integration ofSystems-on-Chip (VLSI-SOC'Ol) December 3-5, 2001, Montpellier, FranceInternational audienceThis paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation