16,374 research outputs found
Power-Aware Speed Scaling in Processor Sharing Systems
Energy use of computer communication systems has quickly become a vital design consideration. One effective method for reducing energy consumption is dynamic speed scaling, which adapts the processing speed to the current load. This paper studies how to optimally scale speed to balance mean response time and mean energy consumption under processor sharing scheduling. Both bounds and asymptotics for the optimal speed scaling scheme are provided. These results show that a simple scheme that halts when the system is idle and uses a static rate while the system is busy provides nearly the same performance as the optimal dynamic speed scaling. However, the results also highlight that dynamic speed scaling provides at least one key benefit - significantly improved robustness to bursty traffic and mis-estimation of workload parameters
Stochastic Analysis of Power-Aware Scheduling
Energy consumption in a computer system can be reduced by dynamic speed scaling, which adapts the processing speed to the current load. This paper studies the optimal way to adjust speed to balance mean response time and mean energy consumption, when jobs arrive as a Poisson process and processor sharing scheduling is used. Both bounds and asymptotics for the optimal speeds are provided. Interestingly, a simple scheme that halts when the system is idle and uses a static rate while the system is busy provides nearly the same performance as the optimal dynamic speed scaling. However, dynamic speed scaling which allocates a higher speed when more jobs are present significantly improves robustness to bursty traffic and mis-estimation of workload parameters
A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems
Recent technological advances have greatly improved the performance and
features of embedded systems. With the number of just mobile devices now
reaching nearly equal to the population of earth, embedded systems have truly
become ubiquitous. These trends, however, have also made the task of managing
their power consumption extremely challenging. In recent years, several
techniques have been proposed to address this issue. In this paper, we survey
the techniques for managing power consumption of embedded systems. We discuss
the need of power management and provide a classification of the techniques on
several important parameters to highlight their similarities and differences.
This paper is intended to help the researchers and application-developers in
gaining insights into the working of power management techniques and designing
even more efficient high-performance embedded systems of tomorrow
Speed-scaling with no Preemptions
We revisit the non-preemptive speed-scaling problem, in which a set of jobs
have to be executed on a single or a set of parallel speed-scalable
processor(s) between their release dates and deadlines so that the energy
consumption to be minimized. We adopt the speed-scaling mechanism first
introduced in [Yao et al., FOCS 1995] according to which the power dissipated
is a convex function of the processor's speed. Intuitively, the higher is the
speed of a processor, the higher is the energy consumption. For the
single-processor case, we improve the best known approximation algorithm by
providing a -approximation algorithm,
where is a generalization of the Bell number. For the
multiprocessor case, we present an approximation algorithm of ratio
improving the best known result by a factor of
. Notice that our
result holds for the fully heterogeneous environment while the previous known
result holds only in the more restricted case of parallel processors with
identical power functions
Synthesis of application specific processor architectures for ultra-low energy consumption
In this paper we suggest that further energy savings can be achieved by a new approach to synthesis of embedded processor cores, where the architecture is tailored to the algorithms that the core executes. In the context of embedded processor synthesis, both single-core and many-core, the types of algorithms and demands on the execution efficiency are usually known at the chip design time. This knowledge can be utilised at the design stage to synthesise architectures optimised for energy consumption. Firstly, we present an overview of both traditional energy saving techniques and new developments in architectural approaches to energy-efficient processing. Secondly, we propose a picoMIPS architecture that serves as an architectural template for energy-efficient synthesis. As a case study, we show how the picoMIPS architecture can be tailored to an energy efficient execution of the DCT algorithm
Energy Efficient Scheduling and Routing via Randomized Rounding
We propose a unifying framework based on configuration linear programs and
randomized rounding, for different energy optimization problems in the dynamic
speed-scaling setting. We apply our framework to various scheduling and routing
problems in heterogeneous computing and networking environments. We first
consider the energy minimization problem of scheduling a set of jobs on a set
of parallel speed scalable processors in a fully heterogeneous setting. For
both the preemptive-non-migratory and the preemptive-migratory variants, our
approach allows us to obtain solutions of almost the same quality as for the
homogeneous environment. By exploiting the result for the
preemptive-non-migratory variant, we are able to improve the best known
approximation ratio for the single processor non-preemptive problem.
Furthermore, we show that our approach allows to obtain a constant-factor
approximation algorithm for the power-aware preemptive job shop scheduling
problem. Finally, we consider the min-power routing problem where we are given
a network modeled by an undirected graph and a set of uniform demands that have
to be routed on integral routes from their sources to their destinations so
that the energy consumption is minimized. We improve the best known
approximation ratio for this problem.Comment: 27 page
- …