2,982 research outputs found

    Shortest path routing algorithm for hierarchical interconnection network-on-chip

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    Interconnection networks play a significant role in efficient on-chip communication for multicore systems. This paper introduces a new interconnection topology called the Hierarchical Cross Connected Recursive network (HCCR) and a shortest path routing algorithm for the HCCR. Proposed topology offers a high degree of regularity, scalability, and symmetry with a reduced number of links and node degree. A unique address encoding scheme is proposed for hierarchical graphical representation of HCCR networks, and based on this scheme a shortest path routing algorithm is devised. The algorithm requires 5(k-1) time where k=logn4-2 and k>0, in worst case to determine the next node along the shortest path

    Entanglement Distribution in Optical Networks

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    The ability to generate entangled photon-pairs over a broad wavelength range opens the door to the simultaneous distribution of entanglement to multiple users in a network by using centralized sources and flexible wavelength-division multiplexing schemes. Here we show the design of a metropolitan optical network consisting of tree-type access networks whereby entangled photon-pairs are distributed to any pair of users, independent of their location. The network is constructed employing commercial off-the-shelf components and uses the existing infrastructure, which allows for moderate deployment costs. We further develop a channel plan and a network-architecture design to provide a direct optical path between any pair of users, thus allowing classical and one-way quantum communication as well as entanglement distribution. This allows the simultaneous operation of multiple quantum information technologies. Finally, we present a more flexible backbone architecture that pushes away the load limitations of the original network design by extending its reach, number of users and capabilities.Comment: 26 pages, 12 figure

    Network on chip architecture for multi-agent systems in FPGA

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    A system of interacting agents is, by definition, very demanding in terms of computational resources. Although multi-agent systems have been used to solve complex problems in many areas, it is usually very difficult to perform large-scale simulations in their targeted serial computing platforms. Reconfigurable hardware, in particular Field Programmable Gate Arrays (FPGA) devices, have been successfully used in High Performance Computing applications due to their inherent flexibility, data parallelism and algorithm acceleration capabilities. Indeed, reconfigurable hardware seems to be the next logical step in the agency paradigm, but only a few attempts have been successful in implementing multi-agent systems in these platforms. This paper discusses the problem of inter-agent communications in Field Programmable Gate Arrays. It proposes a Network-on-Chip in a hierarchical star topology to enable agents’ transactions through message broadcasting using the Open Core Protocol, as an interface between hardware modules. A customizable router microarchitecture is described and a multi-agent system is created to simulate and analyse message exchanges in a generic heavy traffic load agent-based application. Experiments have shown a throughput of 1.6Gbps per port at 100 MHz without packet loss and seamless scalability characteristics

    Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

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    A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs

    Scalability and power consumption of static optical core networks

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    Abstract — A large amount of traffic in core networks is highly aggregated and core nodes are interconnected by high-capacity links. Thus, most of the traffic demands in the core area can be accommodated by providing more or less static connections between ingress and egress nodes. In this paper, we describe and study three particular realizations of static optical core networks and compare them with the dynamic, packet switched architecture based on wavelength-division multiplexing (WDM) transmission and conventional electronic packet routers. We introduce an analytical model for estimating the average number of required switch ports for different network topologies in order to assess both scalability and power consumption of the considered network concepts. The results show that the concept of a static optically transparent core network promises high energy efficiency, and scalability to several tens of nodes. I

    Scalability and power consumption of static optical core networks

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    Abstract — A large amount of traffic in core networks is highly aggregated and core nodes are interconnected by high-capacity links. Thus, most of the traffic demands in the core area can be accommodated by providing more or less static connections between ingress and egress nodes. In this paper, we describe and study three particular realizations of static optical core networks and compare them with the dynamic, packet switched architecture based on wavelength-division multiplexing (WDM) transmission and conventional electronic packet routers. We introduce an analytical model for estimating the average number of required switch ports for different network topologies in order to assess both scalability and power consumption of the considered network concepts. The results show that the concept of a static optically transparent core network promises high energy efficiency, and scalability to several tens of nodes. I
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