Power measurements and analysis for dynamic circuit specialization

Dynamic Circuit Specialization (DCS) is a technique for optimized FPGA implementation and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) provides an opportunity to share the silicon area between different Partially Reconfigurable Modules (PRMs) and therefore results in smaller and faster designs that potentially also reduce the power consumption. In this paper, we show that energy consumption is an important factor that has to be considered while implementing a parameterized design using DCS. In order to make a good choice for implementing a parameterized design with the goal of power optimized implementation, it is important to have a good power consumption estimate of the Dynamic Circuit Specialization. In this context, our paper presents a detailed investigation of the power consumption of a parameterized design implemented using DCS on the Xilinx Zynq-SoC FPGA. We propose an energy analysis of DCS and investigate the benefits of the use of DCS in comparison with a classic static FPGA implementation. We see that the power needed for the reconfiguration is much higher than the gain in power using the reconfiguration over the static implementation. An important reason is because of the CPU involved during the reconfiguration and the interface between the AXI bus and the HWICAP. To reduce the reconfiguration power, we include a clock gating technique to the reconfiguration interface AXI-HWICAP that makes DCS more power efficient. We also relate the power gain to the size of the implementation and to the allowed time to reconfigure versus the useful run time. We conclude that for an implementation with 10 FIR filters, the reconfiguration time should not take more than 30.3% of the total time in order to remain energy efficient. Considering a specific use case with 10 FIR filters at a reconfiguration rate of 0.01, the energy consumption using DCS implementation is 20.5% lower than using the static FIR

Antenna Design for Semi-Passive UHF RFID Transponder with Energy Harvester

A novel microstrip antenna which is dedicated to UHF semi-passive RFID transponders with an energy harvester is presented in this paper. The antenna structure designed and simulated by using Mentor Graphics HyperLynx 3D EM software is described in details. The modeling and simulation results along with comparison with experimental data are analyzed and concluded. The main goal of the project is the need to eliminate a traditional battery form the transponder structure. The energy harvesting block, which is used instead, converts ambient energy (electromagnetic energy of typical radio communication system) into electrical power for internal circuitry. The additional function (gathering extra energy) of the transponder antenna causes the necessity to create new designs in this scope

An Energy and Performance Exploration of Network-on-Chip Architectures

In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be dominated by the data path. This leads to the key result that, if this trend continues, the use of more elaborate control can be justified and will not be immediately limited by the energy budget. A performance analysis also shows that dynamic resource allocation leads to the lowest network latencies, while static allocation may be used to meet QoS goals. Combining the power and performance figures then allows an energy-latency product to be calculated to judge the efficiency of each of the networks. The speculative virtual channel router was shown to have a very similar efficiency to the wormhole router, while providing a better performance, supporting its use for general purpose designs. Finally, area metrics are also presented to allow a comparison of implementation costs

Genuine lab experiences for students in resource constrained environments: The RealLab with integrated intelligent assessment.

Laboratory activities are indispensable for developing engineering skills. Computer Aided Learning (CAL) tools can be used to enhance laboratory learning in various ways, the latest approach being the virtual laboratory technique that emulates traditional laboratory processes. This new approach makes it possible to give students complete and genuine laboratory experiences in situations constrained by limited resources in the provision of laboratory facilities and infrastructure and/or where there is need for laboratory education, for large classes, with only one laboratory stand. This may especially be the case in countries in transition. Most existing virtual laboratories are not available for purchase. Where they are, they may not be cost friendly for resource constrained environments. Also, most do not integrate any form of assessment structure. In this paper, we present a very cost friendly virtual laboratory solution for genuine laboratory experiences in resource constrained environments, with integrated intelligent assessment

Late Innovation Strategies in Asian Electronics Industries: A Conceptual Framework and Illustrative Evidence

This paper was published in Oxford Development Studies special issue in honor of the late Professor Linsu Kim. The paper reviews evidence on the evolution of electronics design in Asia's leading electronics exporting countries, to establish what capabilities have been developed, and to shed light on the forces that are driving "late innovation" strategies. It also reviews intellectual sources that can be used to theoretically ground these hypotheses. Using a well-known taxonomy of innovation that distinguishes incremental, modular, architectural and radical innovations, and the concept of "disruptive technologies", I argue that Asian firms may have realistic chances to engage in incremental innovations as well as in architectural innovations. However, to sustain "late innovation" strategies over a longer period, "complex system integration" capabilities are necessary to provide the missing link.

Domain-general Stroop Performance and Hemispheric Asymmetries: A Resting-state EEG Study

The ability to suppress irrelevant information while executing a task or interference resistance is a function of pFC that is critical for successful goal-directed human behavior. In the study of interference resistance and, more generally, executive functions, two key questions are still open: Does pFC contribute to cognitive control abilities through lateralized but domain-general mechanisms or through hemispheric specialization of domain-specific processes? And what are the underlying causes of interindividual differences in executive control performance? To shed light on these issues, here we employed an interindividual difference approach to investigate whether participants' hemispheric asymmetry in resting-state electrophysiological brain dynamics may reflect their variability in domain-general interference resistance. We recorded participants' resting-state electroencephalographic activity and performed spectral power analyses on the estimated cortical source activity. To measure participants' lateralized brain dynamics at rest, we computed the right-left hemispheric asymmetry score for the \u3b2/\u3b1 power ratio. To measure their domain-general interference resistance ability, verbal and spatial Stroop tasks were used. Robust correlations followed by intersection analyses showed that participants with stronger resting-state-related left-lateralized activity in different pFC regions, namely the mid-posterior superior frontal gyrus, middle and posterior middle frontal gyrus, and inferior frontal junction, were more able to inhibit irrelevant information in both domains. The present results confirm and extend previous findings showing that neurophysiological difference factors may explain interindividual differences in executive functioning. They also provide support for the hypothesis of a left pFC hemispheric specialization for domain-independent phasic cognitive control processes mediating Stroop performance

FPGA structures for high speed and low overhead dynamic circuit specialization

A Field Programmable Gate Array (FPGA) is a programmable digital electronic chip. The FPGA does not come with a predefined function from the manufacturer; instead, the developer has to define its function through implementing a digital circuit on the FPGA resources. The functionality of the FPGA can be reprogrammed as desired and hence the name “field programmable”. FPGAs are useful in small volume digital electronic products as the design of a digital custom chip is expensive. Changing the FPGA (also called configuring it) is done by changing the configuration data (in the form of bitstreams) that defines the FPGA functionality. These bitstreams are stored in a memory of the FPGA called configuration memory. The SRAM cells of LookUp Tables (LUTs), Block Random Access Memories (BRAMs) and DSP blocks together form the configuration memory of an FPGA. The configuration data can be modified according to the user’s needs to implement the user-defined hardware. The simplest way to program the configuration memory is to download the bitstreams using a JTAG interface. However, modern techniques such as Partial Reconfiguration (PR) enable us to configure a part in the configuration memory with partial bitstreams during run-time. The reconfiguration is achieved by swapping in partial bitstreams into the configuration memory via a configuration interface called Internal Configuration Access Port (ICAP). The ICAP is a hardware primitive (macro) present in the FPGA used to access the configuration memory internally by an embedded processor. The reconfiguration technique adds flexibility to use specialized ci rcuits that are more compact and more efficient t han t heir b ulky c ounterparts. An example of such an implementation is the use of specialized multipliers instead of big generic multipliers in an FIR implementation with constant coefficients. To specialize these circuits and reconfigure during the run-time, researchers at the HES group proposed the novel technique called parameterized reconfiguration that can be used to efficiently and automatically implement Dynamic Circuit Specialization (DCS) that is built on top of the Partial Reconfiguration method. It uses the run-time reconfiguration technique that is tailored to implement a parameterized design. An application is said to be parameterized if some of its input values change much less frequently than the rest. These inputs are called parameters. Instead of implementing these parameters as regular inputs, in DCS these inputs are implemented as constants, and the application is optimized for the constants. For every change in parameter values, the design is re-optimized (specialized) during run-time and implemented by reconfiguring the optimized design for a new set of parameters. In DCS, the bitstreams of the parameterized design are expressed as Boolean functions of the parameters. For every infrequent change in parameters, a specialized FPGA configuration is generated by evaluating the corresponding Boolean functions, and the FPGA is reconfigured with the specialized configuration. A detailed study of overheads of DCS and providing suitable solutions with appropriate custom FPGA structures is the primary goal of the dissertation. I also suggest different improvements to the FPGA configuration memory architecture. After offering the custom FPGA structures, I investigated the role of DCS on FPGA overlays and the use of custom FPGA structures that help to reduce the overheads of DCS on FPGA overlays. By doing so, I hope I can convince the developer to use DCS (which now comes with minimal costs) in real-world applications. I start the investigations of overheads of DCS by implementing an adaptive FIR filter (using the DCS technique) on three different Xilinx FPGA platforms: Virtex-II Pro, Virtex-5, and Zynq-SoC. The study of how DCS behaves and what is its overhead in the evolution of the three FPGA platforms is the non-trivial basis to discover the costs of DCS. After that, I propose custom FPGA structures (reconfiguration controllers and reconfiguration drivers) to reduce the main overhead (reconfiguration time) of DCS. These structures not only reduce the reconfiguration time but also help curbing the power hungry part of the DCS system. After these chapters, I study the role of DCS on FPGA overlays. I investigate the effect of the proposed FPGA structures on Virtual-Coarse-Grained Reconfigurable Arrays (VCGRAs). I classify the VCGRA implementations into three types: the conventional VCGRA, partially parameterized VCGRA and fully parameterized VCGRA depending upon the level of parameterization. I have designed two variants of VCGRA grids for HPC image processing applications, namely, the MAC grid and Pixie. Finally, I try to tackle the reconfiguration time overhead at the hardware level of the FPGA by customizing the FPGA configuration memory architecture. In this part of my research, I propose to use a parallel memory structure to improve the reconfiguration time of DCS drastically. However, this improvement comes with a significant overhead of hardware resources which will need to be solved in future research on commercial FPGA configuration memory architectures

Two-photon imaging and analysis of neural network dynamics

The glow of a starry night sky, the smell of a freshly brewed cup of coffee or the sound of ocean waves breaking on the beach are representations of the physical world that have been created by the dynamic interactions of thousands of neurons in our brains. How the brain mediates perceptions, creates thoughts, stores memories and initiates actions remains one of the most profound puzzles in biology, if not all of science. A key to a mechanistic understanding of how the nervous system works is the ability to analyze the dynamics of neuronal networks in the living organism in the context of sensory stimulation and behaviour. Dynamic brain properties have been fairly well characterized on the microscopic level of individual neurons and on the macroscopic level of whole brain areas largely with the help of various electrophysiological techniques. However, our understanding of the mesoscopic level comprising local populations of hundreds to thousands of neurons (so called 'microcircuits') remains comparably poor. In large parts, this has been due to the technical difficulties involved in recording from large networks of neurons with single-cell spatial resolution and near- millisecond temporal resolution in the brain of living animals. In recent years, two-photon microscopy has emerged as a technique which meets many of these requirements and thus has become the method of choice for the interrogation of local neural circuits. Here, we review the state-of-research in the field of two-photon imaging of neuronal populations, covering the topics of microscope technology, suitable fluorescent indicator dyes, staining techniques, and in particular analysis techniques for extracting relevant information from the fluorescence data. We expect that functional analysis of neural networks using two-photon imaging will help to decipher fundamental operational principles of neural microcircuits.Comment: 36 pages, 4 figures, accepted for publication in Reports on Progress in Physic

Multilevel semantic analysis and problem-solving in the flight domain

A computer based cockpit system which is capable of assisting the pilot in such important tasks as monitoring, diagnosis, and trend analysis was developed. The system is properly organized and is endowed with a knowledge base so that it enhances the pilot's control over the aircraft while simultaneously reducing his workload