Communication channel analysis and real time compressed sensing for high density neural recording devices

Next generation neural recording and Brain- Machine Interface (BMI) devices call for high density or distributed systems with more than 1000 recording sites. As the recording site density grows, the device generates data on the scale of several hundred megabits per second (Mbps). Transmitting such large amounts of data induces significant power consumption and heat dissipation for the implanted electronics. Facing these constraints, efficient on-chip compression techniques become essential to the reduction of implanted systems power consumption. This paper analyzes the communication channel constraints for high density neural recording devices. This paper then quantifies the improvement on communication channel using efficient on-chip compression methods. Finally, This paper describes a Compressed Sensing (CS) based system that can reduce the data rate by > 10x times while using power on the order of a few hundred nW per recording channel

Architectures for RF Frequency synthesizers

Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

A 16 x 16 CMOS amperometric microelectrode array for simultaneous electrochemical measurements

There is a requirement for an electrochemical sensor technology capable of making multivariate measurements in environmental, healthcare, and manufacturing applications. Here, we present a new device that is highly parallelized with an excellent bandwidth. For the first time, electrochemical cross-talk for a chip-based sensor is defined and characterized. The new CMOS electrochemical sensor chip is capable of simultaneously taking multiple, independent electroanalytical measurements. The chip is structured as an electrochemical cell microarray, comprised of a microelectrode array connected to embedded self-contained potentiostats. Speed and sensitivity are essential in dynamic variable electrochemical systems. Owing to the parallel function of the system, rapid data collection is possible while maintaining an appropriately low-scan rate. By performing multiple, simultaneous cyclic voltammetry scans in each of the electrochemical cells on the chip surface, we are able to show (with a cell-to-cell pitch of 456 μm) that the signal cross-talk is only 12% between nearest neighbors in a ferrocene rich solution. The system opens up the possibility to use multiple independently controlled electrochemical sensors on a single chip for applications in DNA sensing, medical diagnostics, environmental sensing, the food industry, neuronal sensing, and drug discovery

Active C4 electrodes for local field potential recording applications

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μV rms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented.R01 NS072385 - NINDS NIH HHS; 1R01 NS072385 - NINDS NIH HH

Magneto-inductive Passive Relaying in Arbitrarily Arranged Networks

We consider a wireless sensor network that uses inductive near-field coupling for wireless powering or communication, or for both. The severely limited range of an inductively coupled source-destination pair can be improved using resonant relay devices, which are purely passive in nature. Utilization of such magneto-inductive relays has only been studied for regular network topologies, allowing simplified assumptions on the mutual antenna couplings. In this work we present an analysis of magneto-inductive passive relaying in arbitrarily arranged networks. We find that the resulting channel has characteristics similar to multipath fading: the channel power gain is governed by a non-coherent sum of phasors, resulting in increased frequency selectivity. We propose and study two strategies to increase the channel power gain of random relay networks: i) deactivation of individual relays by open-circuit switching and ii) frequency tuning. The presented results show that both methods improve the utilization of available passive relays, leading to reliable and significant performance gains.Comment: 6 pages, 9 figures. To be presented at the IEEE International Conference on Communications (ICC), Paris, France, May 201

Modelling and thermal analysis of a seismic borehole sensor: diploma 2015

Analysis and adaptation of an acquisition system for a seismometer to enable operation at high temperatures (up to 180 [°C]). The simulation software and thermal measurements are used to validate theoretical results

Capacitance-to-Digital Converter for Ultra-Low-Power Wireless Sensor Nodes

Power consumption is one of the main design constraints in today’s integrated circuits. For systems like wearable electronics, UAVs, IOT systems powered by batteries which are charged using the energy harvested from various sources like RF, Thermal, Solar and Vibration, ultra-low power consumption is paramount. In these systems, Transducers which convert physical parameters into electrical parameters and the analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power signal Front End used in several low power electronic systems in general and pressure measurement systems in particular. In this thesis, Capacitance to Digital Converter based pressure measurement system has been implemented. Here we present a general-purpose, wide-range CDC that combines a correlated double sampling (CDS) approach with a differential asynchronous SAR ADC. Since the sensor capacitor is sampled only twice per conversion, energy per conversion is low. Furthermore, since the CDS separates the sensor capacitor from the CDAC, a full differential input voltage range is preserved. The CDC has a 2.5-to-75.5pF conversion range. Monotonic SAR ADC was designed in 180nm CMOS with 1-V power supply and a 1-kS/s sampling rate with switching energy of about 100nW

Wireless sensors and IoT platform for intelligent HVAC control

Energy consumption of buildings (residential and non-residential) represents approximately 40% of total world electricity consumption, with half of this energy consumed by HVAC systems. Model-Based Predictive Control (MBPC) is perhaps the technique most often proposed for HVAC control, since it offers an enormous potential for energy savings. Despite the large number of papers on this topic during the last few years, there are only a few reported applications of the use of MBPC for existing buildings, under normal occupancy conditions and, to the best of our knowledge, no commercial solution yet. A marketable solution has been recently presented by the authors, coined the IMBPC HVAC system. This paper describes the design, prototyping and validation of two components of this integrated system, the Self-Powered Wireless Sensors and the IOT platform developed. Results for the use of IMBPC in a real building under normal occupation demonstrate savings in the electricity bill while maintaining thermal comfort during the whole occupation schedule.QREN SIDT [38798]; Portuguese Foundation for Science & Technology, through IDMEC, under LAETA [ID/EMS/50022/2013