Digital Signal Processor Based Real-Time Phased Array Radar Backend System and Optimization Algorithms

This dissertation presents an implementation of multifunctional large-scale phased array radar based on the scalable DSP platform. The challenge of building large-scale phased array radar backend is how to address the compute-intensive operations and high data throughput requirement in both front-end and backend in real-time. In most of the applications, FPGA or VLSI hardware are typically used to solve those difficulties. However, with the help of the fast development of IC industry, using a parallel set of high-performing programmable chips can be an alternative. We present a hybrid high-performance backend system by using DSP as the core computing device and MTCA as the system frame. Thus, the mapping techniques for the front and backend signal processing algorithm based on DSP are discussed in depth. Beside high-efficiency computing device, the system architecture would be a major factor influencing the reliability and performance of the backend system. The reliability requires the system must incorporate the redundancy both in hardware and software. In this dissertation, we propose a parallel modular system based on MTCA chassis, which can be reliable, scalable, and fault-tolerant. Finally, we present an example of high performance phased array radar backend, in which there is the number of 220 DSPs, achieving 7000 GFLOPS calculation from 768 channels. This example shows the potential of using the combination of DSP and MTCA as the computing platform for the future multi-functional large-scale phased array radar

Middleware ALOE for DSP TMS320C6455

The starting aim of this project is to give more flexibility to the 4th mobile generation systems. Since reconfigurable-reprogrammable systems are becoming each time more widespread in the communications system implementations, it is set out to analyze those mechanisms of the current processor devices (DSPs) that have high importance when flexibility has to be provided to the system management. This way, the ALOE middleware - used in Software Radio - is ported from its original x86 computer running Linux to the DSP processors from Texas Instruments. Meanwhile, the Ethernet interface that the DSP provides is evaluated with the objective of its characterization in real time environments

Methods for Control, Calibration, and Performance Optimization of Phased Array Systems

Phased array radar systems have proven advantageous in a variety of research applications, offering faster volume scans and unparalleled time-resolution as compared to traditional parabolic dish antenna systems that rely solely on mechanical systems for controlling the direction of radiation. As such, research has accelerated the development of practical phased array systems to realize their full vision. In particular, next generation phased array systems aim to provide additional advantages in the form of re-configurable beam patterns, adaptive digital beamforming, multiple-input multiple-output (MIMO) radar modes, and other software-defined technologies. However, to fully realize a paradigm shift in phased array technology, especially as the ratio of array to sub-array size becomes greater, this requires a corresponding increase in novel digital backend architectures to fully achieve this vision. Therefore, new methods for control, calibration, and performance optimization are required to enable next-generation phased array systems to reach their potential. In this thesis, a variety of practical engineering challenges related to phased array system design are discussed, with system-level implications and relevant theory included where necessary. For instance, for the first time, as explained in this thesis, a GPS disciplined, time-interleaved measurement technique that leveraged real-time control of a beamformer was developed to enable accurate post-processing correction of the phase drift that results from clocking differences between noncoherent physically separated bistatic nodes. In addition, laboratory efficacy of digital predistortion using the memory-polynomial model has been confirmed for the purpose of maximizing an element's usable power while minimizing spectral spreading and achieving desirable output linearity during operation, and a novel method for training predistortion models comprised of a combined software-defined and physical mechanism for measuring transmitter front-end distortion for elements within a digital-at-every element array has been proposed and verified in the lab

Media gateway utilizando um GPU

Mestrado em Engenharia de Computadores e Telemátic