Protein dissection approach as a powerful tool to identify new potential drugs

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid, Facultad de Medicina, Departamento de Medicina. Fecha de lectura: 20-05-2020Esta tesis tiene embargado el acceso al texto completo hasta el 20-11-202

Batteries and Supercapacitors Aging

Electrochemical energy storage is a key element of systems in a wide range of sectors, such as electro-mobility, portable devices, and renewable energy. The energy storage systems (ESSs) considered here are batteries, supercapacitors, and hybrid components such as lithium-ion capacitors. The durability of ESSs determines the total cost of ownership, the global impacts (lifecycle) on a large portion of these applications and, thus, their viability. Understanding ESS aging is a key to optimizing their design and usability in terms of their intended applications. Knowledge of ESS aging is also essential to improve their dependability (reliability, availability, maintainability, and safety). This Special Issue includes 12 research papers and 1 review article focusing on battery, supercapacitor, and hybrid capacitor aging

Heat Transfer in Engineering

The advancements in research related to heat transfer has gathered much attention in recent decades following the quest for efficient thermal systems, interdisciplinary studies involving heat transfer, and energy research. Heat transfer, a fundamental transport phenomenon, has been considered one of the critical aspects for the development and advancement of many modern applications, including cooling, thermal systems which contain symmetry analysis, energy conservation and storage, and symmetry-preserving discretization of heat transfer in a complex turbulent flow. The objective of this book is to present recent advances, as well as up-to-date progress in all areas of heat transfer in engineering and its influence on emerging technologies

sCAM: An Untethered Insertable Laparoscopic Surgical Camera Robot

Fully insertable robotic imaging devices represent a promising future of minimally invasive laparoscopic vision. Emerging research efforts in this field have resulted in several proof-of-concept prototypes. One common drawback of these designs derives from their clumsy tethering wires which not only cause operational interference but also reduce camera mobility. Meanwhile, these insertable laparoscopic cameras are manipulated without any pose information or haptic feedback, which results in open loop motion control and raises concerns about surgical safety caused by inappropriate use of force.This dissertation proposes, implements, and validates an untethered insertable laparoscopic surgical camera (sCAM) robot. Contributions presented in this work include: (1) feasibility of an untethered fully insertable laparoscopic surgical camera, (2) camera-tissue interaction characterization and force sensing, (3) pose estimation, visualization, and feedback with sCAM, and (4) robotic-assisted closed-loop laparoscopic camera control. Borrowing the principle of spherical motors, camera anchoring and actuation are achieved through transabdominal magnetic coupling in a stator-rotor manner. To avoid the tethering wires, laparoscopic vision and control communication are realized with dedicated wireless links based on onboard power. A non-invasive indirect approach is proposed to provide real-time camera-tissue interaction force measurement, which, assisted by camera-tissue interaction modeling, predicts stress distribution over the tissue surface. Meanwhile, the camera pose is remotely estimated and visualized using complementary filtering based on onboard motion sensing. Facilitated by the force measurement and pose estimation, robotic-assisted closed-loop control has been realized in a double-loop control scheme with shared autonomy between surgeons and the robotic controller.The sCAM has brought robotic laparoscopic imaging one step further toward less invasiveness and more dexterity. Initial ex vivo test results have verified functions of the implemented sCAM design and the proposed force measurement and pose estimation approaches, demonstrating the technical feasibility of a tetherless insertable laparoscopic camera. Robotic-assisted control has shown its potential to free surgeons from low-level intricate camera manipulation workload and improve precision and intuitiveness in laparoscopic imaging

Improvement of consistency, accuracy and interpretation of characterisation test techniques for Li-ion battery cells for automotive application

Equivalent circuit models (ECM) are required to provide an on-board model of battery behaviour by battery management systems (BMS). The performance of ECMs is dependent on characterisation test results. The components of the ECM are commonly parameterised using electrochemical impedance spectroscopy (EIS) results, open circuit voltage (OCV) test results, and capacity test results. Therefore, these three tests are important for ECM parameterisation. Although the test procedures for these characterisation tests exist to test Li-ion cells for a range of applications e.g. portable electronic devices, they fail to provide essential information for automotive application due to the different requirements of vehicles (e.g. high power and energy, wide operating environment, long service life). This thesis reports research to improve consistency, accuracy and interpretation of characterisation test techniques for Li-ion battery cells for automotive application. The capacity of the battery pack is a vital parameter required for an ECM to estimate driving range. Existing techniques for predicting the driving range of an electric vehicle use the capacity value in Amp-hours, measured by existing capacity test techniques. In this thesis, experimental evidence that establishes the advantages of using capacity in Watt-hours instead of the capacity in Amp-hours as per the standard test is presented for the first time. Moreover, it is reported that measured battery capacity can vary by up to 5.0 % depending on the length of intermediate rest period. The OCV is another crucial parameter of ECM. The path dependence of OCV is a distinctive characteristic of Li-ion batteries which is known as OCV hysteresis. OCV test procedures used previously do not consider the initial conditions of the cells and capacity variations that show a change in OCV, leading to an apparent increase in, or erroneous, hysteresis. Using a new methodology which addresses issues mentioned above, OCV and OCV hysteresis has been quantified for different Li-ion cells for the first time. The test results show that a battery’s OCV is directly related to the discharge capacity, not the more commonly used SoC. The maximum hysteresis was found in a LiFePO4 (LFP) cell and lowest in a LTO cell, although still measurable. A dynamic hysteresis model is used to show how better OCV prediction accuracy can be achieved by a BMS when hysteresis voltage is a function of SoC instead of assuming it to be a constant, as traditionally done. EIS is commonly used to parameterise an ECM. For the first time this thesis reports that the time period between the removal of an electrical load and an EIS measurement affects the results. The study of five commercially available cells of varying capacities and electrode chemistries show that, regardless of the cell type, the maximum impedance change takes place within the first 4 hours of the relaxation period. Therefore a standardised relaxation period of minimum 4 hours should be allowed before performing EIS test. In addition to ECM parameterisation, EIS has been considered for online measurement, integrated with a BMS. This thesis concluded that the use of EIS as a fast measurement tool will be unreliable because of the relaxation effect. The flaws with capacity, EIS and OCV tests for automotive applications have been discussed. Through experimental evidence and electrochemical explanation it has been demonstrated that these tests can be made more consistent (e.g. by allowing fixed relaxation period in EIS test), have improved accuracy (e.g. incorporating hysteresis as a function of SoC) and better interpretation of test results (e.g. Watt-hours instead of Amp-hours in capacity test) are possible. Therefore, the overall contributions of this thesis to the scientific community are better consistency, accuracy and interpretation of these three tests. With the use of a case study, it has been shown that this new knowledge will improve performance of ECM, and thus BMS. This is not only for automotive but also more general applications through adopting the proposed new methodologies

Sixth Goddard Conference on Mass Storage Systems and Technologies Held in Cooperation with the Fifteenth IEEE Symposium on Mass Storage Systems

This document contains copies of those technical papers received in time for publication prior to the Sixth Goddard Conference on Mass Storage Systems and Technologies which is being held in cooperation with the Fifteenth IEEE Symposium on Mass Storage Systems at the University of Maryland-University College Inn and Conference Center March 23-26, 1998. As one of an ongoing series, this Conference continues to provide a forum for discussion of issues relevant to the management of large volumes of data. The Conference encourages all interested organizations to discuss long term mass storage requirements and experiences in fielding solutions. Emphasis is on current and future practical solutions addressing issues in data management, storage systems and media, data acquisition, long term retention of data, and data distribution. This year's discussion topics include architecture, tape optimization, new technology, performance, standards, site reports, vendor solutions. Tutorials will be available on shared file systems, file system backups, data mining, and the dynamics of obsolescence

Profilage, caractérisation et partitionnement fonctionnel dans une plate-forme de conception de systèmes embarqués

RÉSUMÉ La complexité architecturale des systèmes embarqués augmente constamment et ceux-ci comprennent maintenant plusieurs processeurs, bus, périphériques et accélérateurs matériels. Les méthodologies présentement utilisées par l'industrie pour la conception des systèmes embarqués n'arrivent pas à suivre cette évolution. Des méthodologies de niveau système ont été proposées pour hausser le niveau d'abstraction de la conception des systèmes embarqués. Une telle méthodologie comporte une plate-forme virtuelle qui permet d'allouer des composants, d'y assigner la fonctionnalité de l'application et de simuler l'architecture résultante à un niveau transactionnel. Une méthodologie de niveau système peut accélérer la conception des systèmes embarqués en partant d'une spécification exécutable, en explorant automatiquement l'espace de conception et en synthétisant une architecture optimisée pour l'application. Cependant, les méthodologies de niveau système existantes ont plusieurs lacunes. Elles supposent typiquement que l'application est modélisée avec un modèle de calcul restrictif et n'automatisent pas la synthèse des modules de l'application vers des blocs matériels. Elles n'intègrent pas un profilage non-intrusif de l'application ou d'une architecture qui l'implémente. Leurs méthodes d'estimation n'automatisent pas la caractérisation de l'application ou de la plate-forme. Ces méthodologies considèrent séparément les problèmes de l'allocation des processeurs, de l'assignation des tâches aux processeurs et du choix d'une topologie de communication. Nous présentons une méthodologie de niveau système pour la conception, l'exploration architecturale et la synthèse des systèmes embarqués basée sur la technologie Space Code- sign� et sa plate-forme virtuelle SPACE. Cette méthodologie répond aux problématiques soulevées car elle combine un modèle de calcul plus expressif, une méthode de synthèse matérielle automatisée des modules d'une spécification SystemC, un profilage non-intrusif au niveau système, une méthode de caractérisation automatisée de l'application et du système d'exploitation temps-réel (RTOS), ainsi que des heuristiques pour une formulation unifiée du problème d'exploration architecturale. Ainsi, nous avons défini pour notre méthodologie un nouveau modèle de calcul, les réseaux de processus temps-réel (RTPN) qui sont une extension des réseaux de processus Kahn. Cette extension permet de modéliser des aspects importants du traitement temps-réel tels que la scrutation, les senseurs échantillonnés, les périphériques d'entrée/sortie et les contraintes temps-réel. La sémantique dénotationnelle des RTPN est définie afin de vérifier si le raffinement d'une spécification exécutable SystemC vers une implémentation concrète est fonctionnellement correct. Notre méthodologie inclut une méthode automatisée de raffinement des communications transactionnelles vers des protocoles précis au cycle et à la broche près ainsi que la génération automatique de blocs matériels pour les modules de l'application. Cette méthode permet, conjointement avec une méthode de génération de code embarqué incluant un RTOS, de générer une implémentation de l'application qui peut être simulée avec la plate-forme virtuelle ou synthétisée et exécutée sur la cible finale. Une nouvelle méthode de profilage au niveau système est appliquée à une telle simulation, ce qui permet d'extraire non-intrusivement des données sur la performance des modules, des processeurs, du RTOS, des bus et des mémoires. Une nouvelle méthode automatisée permet de caractériser, par des simulations profilées, à la fois la fonctionnalité de l'application et les implémentations logicielles et matérielles de ses modules. Les périphériques et les bus de la plate-forme virtuelle ont également été caractérisées et une nouvelle méthode automatise la caractérisation du RTOS. Ces caractérisations configurent un simulateur de performance à haut niveau qui estime précisément et très rapidement la performance d'un ensemble d'architectures pour l'application en tenant compte de la contention sur les bus et de l'ordonnancement des tâches sur les processeurs. Cette caractérisation mène également à une estimation précise et rapide des besoins en ressources matérielles. Nous présentons une formulation du problème d'exploration architecturale qui combine le partitionnement logiciel/matériel, l'allocation des processeurs, l'assignation des tâches aux processeurs et le choix d'une topologie de communication. L'exploration architecturale évalue les architectures selon des critères de performance et de coût matériel à l'aide de notre méthode d'estimation. Nous présentons pour la première fois une analyse combinatoire de ce problème et sa formulation comme un problème de recherche locale, pour la résolution duquel nous définissons des heuristiques basées sur un recuit simulé adaptatif et sur une recherche tabou réactive. L'architecture retenue par l'exploration architecturale peut ensuite être synthétisée vers une implémentation finale dans un flot de conception RTL bien établi. La méthodologie dans son ensemble est appliquée à trois études de cas : un système de guidage d'un astromobile, un décodeur JPEG avec détection de peau et un encodeur/décodeur WiMAX. ----------ABSTRACT Embedded systems have increasingly complex architectures and are now composed of several processors, buses, peripherals and hardware accelerators. Embedded system design methodologies currently used in industry are not keeping up with this evolution. System-level methodologies have been proposed in order to raise the level of abstraction of embedded system design. Such a methodology includes a virtual platform in which components can be allocated while application tasks can be bound to allocated components for a transaction-level simulation of the resulting architecture. A system-level methodology can accelerate embedded system design by using an executable specification, automating design space exploration and synthesizing an optimized architecture for the application. However, current system-level methodologies have several shortcomings. They typically assume that the application is modeled with a restrictive model of computation and do not automate the synthesis of hardware blocks from application modules. They do not support a non-intrusive profiling of the application or of an architecture implementing the application. Their estimation methods do not automate the characterization of the application or of the platform. These methodologies consider processor allocation, task binding to processors and the choice of a communication topology to be separate problems instead of being different aspects of a single problem. We present a system-level methodology for the design, architectural exploration and synthesis of embedded systems based on the Space Codesign� technology and its SPACE virtual platform. This methodology tackles these problems by combining a more expressive model of computation, a method for the automated synthesis of hardware blocks from a SystemC specification's modules, a non-intrusive system-level profiling, a method for the automated characterization of the application and of the real-time operating system (RTOS), as well as heuristics for a unified formulation of the architectural exploration problem. We have thus defined for our methodology a novel model of computation, called real-time process networks (RTPN), which is an extension of Kahn process networks. This extension enables the modeling of important aspects of real-time processing, such as polling, sensor sampling, input/output peripherals and real-time constraints. We define the denotational semantics of RTPNs, which is used to verify the functional correctness of a refinement from a SystemC executable specification to a concrete implementation. Our methodology includes an automated refinement from transaction-level communications to cycle- and pin-accurate protocols as well as an automated generation of hardware blocks from application modules. This method enables, when combined with an embedded software generation method which includes a RTOS, the generation of an implementation of the application, which can be simulated with the virtual platform or synthesized and executed on the final target. A novel profiling method is applied to such simulations in order to non-intrusively extract data on the performance of modules, processors, RTOS, buses and memories. A novel automated method characterizes, through profiled simulations, both the application functionality and the software and hardware implementations of its modules. The devices and buses of the virtual platform have also been characterized and a novel method automates the characterization of the RTOS. These characterizations configure a high-level performance simulator for an accurate and very fast estimation of the performance of several candidate architectures for the application, taking into account bus contention and task scheduling on processors. This characterization also powers a fast and accurate estimation of required hardware resources. A formulation of the architectural exploration problem is given such that it combines hardware/software partitioning, processor allocation, task binding on processors and the selection of a communication topology. This architectural exploration evaluates architectures for criteria of performance and hardware cost with our estimation method. We present for the first time a combinatorial analysis of this problem and its formulation as a local search problem, for which heuristics based on adaptative simulated annealing and reactive tabu search are defined. The architecture selected by the architectural exploration can then be synthesized towards a final implementation in a well-established RTL design flow. The methodology as a whole has been applied to three case studies: a rover guiding system, a JPEG decoder with skin detection and a WiMAX encoder/decoder

Second Annual Workshop on Space Operations Automation and Robotics (SOAR 1988)

Papers presented at the Second Annual Workshop on Space Operation Automation and Robotics (SOAR '88), hosted by Wright State University at Dayton, Ohio, on July 20, 21, 22, and 23, 1988, are documented herein. During the 4 days, approximately 100 technical papers were presented by experts from NASA, the USAF, universities, and technical companies. Panel discussions on Human Factors, Artificial Intelligence, Robotics, and Space Systems were held but are not documented herein. Technical topics addressed included knowledge-based systems, human factors, and robotics

Nouvelles Architectures Hybrides (Logique / Mémoires Non-Volatiles et technologies associées.)

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants.Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF