257,134 research outputs found
Power-constrained block-test list scheduling
A list scheduling approach is proposed in this paper to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is also used in combination with the list scheduling algorithm in order to improve the test concurrency, having assigned power dissipation limits. Moreover, the algorithm features a power dissipation balancing provision. Test scheduling examples are discussed, highlighting further research steps towards an efficient system-level test scheduling algorith
Ultra-Low-Power Superconductor Logic
We have developed a new superconducting digital technology, Reciprocal
Quantum Logic, that uses AC power carried on a transmission line, which also
serves as a clock. Using simple experiments we have demonstrated zero static
power dissipation, thermally limited dynamic power dissipation, high clock
stability, high operating margins and low BER. These features indicate that the
technology is scalable to far more complex circuits at a significant level of
integration. On the system level, Reciprocal Quantum Logic combines the high
speed and low-power signal levels of Single-Flux- Quantum signals with the
design methodology of CMOS, including low static power dissipation, low latency
combinational logic, and efficient device count.Comment: 7 pages, 5 figure
A combined tree growing technique for block-test scheduling under power constraints
A tree growing technique is used here together with classical scheduling algorithms in order to improve the test concurrency having assigned power dissipation limits. First of all, the problem of unequal-length block-test scheduling under power dissipation constraints is modeled as a tree growing problem. Then a combination of list and force-directed scheduling algorithms is adapted to tackle it. The goal of this approach is to achieve rapidly a test scheduling solution with a near-optimal test application time. This is initially achieved with the list approach. Then the power dissipation distribution of this solution is balanced by using a force-directed global priority function. The force-directed priority function is a distribution-graph based global priority function. A constant additive model is employed for power dissipation analysis and estimation. Based on test scheduling examples, the efficiency of this approach is discussed as compared to the other approaches
A comparison of classical scheduling approaches in power-constrained block-test scheduling
Classical scheduling approaches are applied here to overcome the problem of unequal-length block-test scheduling under power dissipation constraints. List scheduling-like approaches are proposed first as greedy algorithms to tackle the fore mentioned problem. Then, distribution-graph based approaches are described in order to achieve balanced test concurrency and test power dissipation. An extended tree growing technique is also used in combination with these classical approaches in order to improve the test concurrency having assigned power dissipation limits. A comparison between the results of the test scheduling experiments highlights the advantages and disadvantages of applying different classical scheduling algorithms to the power-constrained test scheduling proble
Design of A Low Power Low Voltage CMOS Opamp
In this paper a CMOS operational amplifier is presented which operates at 2V
power supply and 1microA input bias current at 0.8 micron technology using non
conventional mode of operation of MOS transistors and whose input is depended
on bias current. The unique behaviour of the MOS transistors in subthreshold
region not only allows a designer to work at low input bias current but also at
low voltage. While operating the device at weak inversion results low power
dissipation but dynamic range is degraded. Optimum balance between power
dissipation and dynamic range results when the MOS transistors are operated at
moderate inversion. Power is again minimised by the application of input
dependant bias current using feedback loops in the input transistors of the
differential pair with two current substractors. In comparison with the
reported low power low voltage opamps at 0.8 micron technology, this opamp has
very low standby power consumption with a high driving capability and operates
at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more
than other low power low voltage opamps reported at 0.8 um technology [1,2].
Vittoz at al [3] reported that slew rate can be improved by adaptive biasing
technique and power dissipation can be reduced by operating the device in weak
inversion. Though lower power dissipation is achieved the area required by the
circuit is very large and speed is too small. So, operating the device in
moderate inversion is a good solution. Also operating the device in
subthreshold region not only allows lower power dissipation but also a lower
voltage operation is achieved.Comment: 8 Pages, VLSICS Journa
- …