Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates

Power modeling techniques have traditionally neglected the main part of the energy consumed in the internal nodes of static CMOS gates: the power dissipated by input transitions that do not produce output switching. In this work, we present an experimental set-up that shows that this power component may contribute up to 59% of the total power consumption of a gate in modern technologies. This fact makes very important to include it into any accurate power modelMinisterio de Educación y Ciencia HYPER MIC TEC2007-6180

IDPAL – A Partially-Adiabatic Energy-Efficient Logic Family: Theory and Applications to Secure Computing

Low-power circuits and issues associated with them have gained a significant amount of attention in recent years due to the boom in portable electronic devices. Historically, low-power operation relied heavily on technology scaling and reduced operating voltage, however this trend has been slowing down recently due to the increased power density on chips. This dissertation introduces a new very-low power partially-adiabatic logic family called Input-Decoupled Partially-Adiabatic Logic (IDPAL) with applications in low-power circuits. Experimental results show that IDPAL reduces energy usage by 79% compared to equivalent CMOS implementations and by 25% when compared to the best adiabatic implementation. Experiments ranging from a simple buffer/inverter up to a 32-bit multiplier are explored and result in consistent energy savings, showing that IDPAL could be a viable candidate for a low-power circuit implementation. This work also shows an application of IDPAL to secure low-power circuits against power analysis attacks. It is often assumed that encryption algorithms are perfectly secure against attacks, however, most times attacks using side channels on the hardware implementation of an encryption operation are not investigated. Power analysis attacks are a subset of side channel attacks and can be implemented by measuring the power used by a circuit during an encryption operation in order to obtain secret information from the circuit under attack. Most of the previously proposed solutions for power analysis attacks use a large amount of power and are unsuitable for a low-power application. The almost-equal energy consumption for any given input in an IDPAL circuit suggests that this logic family is a good candidate for securing low-power circuits again power analysis attacks. Experimental results ranging from small circuits to large multipliers are performed and the power-analysis attack resistance of IDPAL is investigated. Results show that IDPAL circuits are not only low-power but also the most secure against power analysis attacks when compared to other adiabatic low-power circuits. Finally, a hybrid adiabatic-CMOS microprocessor design is presented. The proposed microprocessor uses IDPAL for the implementation of circuits with high switching activity (e.g. ALU) and CMOS logic for other circuits (e.g. memory, controller). An adiabatic-CMOS interface for transforming adiabatic signals to square-wave signals is presented and issues associated with a hybrid implementation and their solutions are also discussed

An adiabatic charge pump based charge recycling design style

A typical CMOS gate draws charge equal to C[subscript L]Vdd2 from the power supply (Vdd) where C[subscript L] is the load capacitance. Half of the energy is dissipated in the pull-up p-type network, and the other half is dissipated in the pull-down n-type network. Adiabatic CMOS circuit reduces the dissipated energy by providing the charge at a rate significantly lower than the inherent RC delay of the gate. The charge can also be recovered with an RLC oscillator based power supply. However, the two main problems with adiabatic design style are the design of a high frequency RLC oscillator for the power supply, and the need to slow down the rate of charge supply for lower energy. This reduction in speed of operation renders this adiabatic technique inapplicable in certain situations. A new approach incorporating an adiabatic charge pump that moves the slower adiabatic components away from the critical path of the logic is proposed in this work. The adiabatic delays of a charge pump are overlapped with the computing path logic delays. Hence, the proposed charge pump based recycling technique is especially effective for pipelined datapath computations (digital signal processing, DSP, is such a domain) where timing considerations are important. Also the proposed design style does not interfere with the critical path of the system, and hence the delay introduced by this scheme does not reduce the overall computational speed. In this work, we propose one implementation schema that involves tapping the ground-bound charge in a capacitor (virtual ground) and using an adiabatic charge-pump circuit to feed internal virtual power supplies. As the design relies on leakage charge to generate virtual power supplies, it is most effective in large circuits that undergo considerable switching activity resulting in substantial charge tapping by the proposed scheme. The proposed method has been implemented in DSP applications like FIR filter, DCT/IDCT filters and FFT filters. Simulations results in SPICE indicate that the proposed scheme reduces energy consumption in these DSP circuits by as much as 18% with no loss in performance, paving way for a new approach towards conserving energy in complex digital systems

Low Power Digital Design using Asynchronous Logic

This thesis summarizes research undertaken at San José State University between January 2009 and May 2011, which introduces a new method of achieving low power by reducing the dependency of the clock signal in the design. A clock signal consumes power even when the circuit is idle, but asynchronous circuits by default move into the idle state and involve no transition in the circuit during that state. In addition, in an active system, only the subsystem that is in use dissipates power. This work mainly focused on obtaining low power by implementing asynchronous logic. The work also studied the measure of power consumption using asynchronous logic by designing a simple Display Controller. The Display Controller was designed using Verilog HDL and synthesized using Synopsys Design Compiler. The work also studied the trade–offs in power, area, and design complexity in asynchronous design. The power consumed by the synchronous and asynchronous display controllers was measured, and the asynchronous design consumed about 17% less power than its synchronous counterpart. The area of the asynchronous design was twice that of the synchronous one. Power can be reduced by reducing the dependency of the clock signal in the design by choosing asynchronous logic

Cryogenic Control Beyond 100 Qubits

Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine