Multi-Stream LDPC Decoder on GPU of Mobile Devices

Low-density parity check (LDPC) codes have been extensively applied in mobile communication systems due to their excellent error correcting capabilities. However, their broad adoption has been hindered by the high complexity of the LDPC decoder. Although to date, dedicated hardware has been used to implement low latency LDPC decoders, recent advancements in the architecture of mobile processors have made it possible to develop software solutions. In this paper, we propose a multi-stream LDPC decoder designed for a mobile device. The proposed decoder uses graphics processing unit (GPU) of a mobile device to achieve efficient real-time decoding. The proposed solution is implemented on an NVIDIA Tegra board as a system on a chip (SoC), where our results indicate that we can control the load on the central processing units through the multi-stream structure

Fifth Generation (5G) New Radio (NR) Channel Codes Contenders Based on Field- Programmable Gate Arrays (FPGA): A Review Paper

ان الحاجة المتزايدة على الجودة، مثل السرعة العالية والتاخير المنخفض والتغطية الواسعة واستهلاك الطاقة والتكلفة والاتصالات الموثوقة في خدمات الهاتف المحمول والوسائط المتعددة ونقل البيانات تفرض استخدام المتطلبات التقنية المتقدمة في الجيل الخامس (5G) الإذاعة الجديدة (NR). واحدة من أهم الأجزاء في الطبقة المادية للجيل الجديد هي تقنية الترميز لتصحيح الأخطاء. هنالك ثلاثة اشكال مقترحة لتقنيات الترميز المخصصة لقنوات نقل البيانات وقنوات التحكم هي  الترميز التوربيني وفحص التكافؤ المنخفض الكثافة (LDPC) والرموز القطبية. يتم تقييم المنافسة بين هذه الانواع من حيث القدرة على تصحيح الأخطاء والتعقيد الحسابي والمرونة. التوازي والمرونة وسرعة المعالجة العالية لمصفوفة البوابة القابلة للبرمجة الميدانية (FPGA) تجعلها أفضل في النماذج الأولية وتنفيذ الرموز المختلفة. تقدم هذه الورقة دراسة استقصائية للبحوث الحالية التي تتعامل مع تصميم وحدة فك الترميز المستندة إلى FPGA المرتبطة برموز القناة المذكورة سابقًا.The increased demands for quality, like high throughput, low-latency, wide coverage, energy consumption, cost and reliable connections in mobile services, multimedia and data transmission impose the use of advance technical requirements for the next fifth-generation (5G) new radio (NR). One of the most crucial parts in the physical layer of the new generation is the error correction coding technique. Three schemes, namely; Turbo, low density parity check (LDPC), and polar codes are potentially ‎considered as the candidate codes for both data and control channels. The competition is evaluated in terms of error correction capability, computational complexity, and flexibility. The parallelism, flexibility and high processing speed of Field-Programmable Gate Array (FPGA) make it preferable in prototyping and implementation of different codes. This paper presents a survey on the current literatures that deals with FPGA-based decoder design associated with the previously mentioned channel codes

Energy Performance of LDPC Scheme in Multi-Hop Wireless Sensor Network with Two base Stations Model

Conservation of the energy is one of the main design issues in wireless sensor networks. The limited battery power of each sensor node is a challenging task in deploying this type of network. The challenge is crucial in reliable wireless network when implementing efficient error correcting scheme with energy consuming routing protocol. In this work, we investigated the energy performance of LDPC code in multi-hop wireless sensor network. We proposed a model of two base stations to prolong the lifetime and build a reliable and energy-efficient network. Through performed MATLAB simulations, we examine the energy effectiveness of multiple base stations model on reliable wireless sensor network performance in different network dimensions