A Low-power CMOS 2-PPM Demodulator for Energy Detection IR-UWB Receivers

This paper presents an integrated 2-PPM CMOS demodulator for non-coherent energy detection receivers which inherently provides analog-to-digital conversion. The device, called Bi-phase integrator, employs an open loop Gm - C integrator loaded with a switched capacitor network. The circuit has been simulated in a mixed-mode UMC 0.18mum technology and its performance figures are obtained through a mixed-signal simulation environment developed with the aid of ADVanceMS (ADMS, mentor graphics). Bit-error-rate simulations show that the circuit performance is about the same of an ideal energy detection receiver employing infinite quantization resolution. In addition, the simulations show that the circuit provides a complete offset rejection. Thanks to its low power consumption (1 mW during demodulation), its application is appealing for portable devices which aim at very low-power consumption

Tunable class AB CMOS Gm-C channel filter for a bluetooth zero-IF receiver

A novel tunable third order low-pass Gm-C filter is introduced. Programmable transconductors operating in class AB have been used for its implementation hence featuring low quiescent power consumption. The operation in class AB is achieved using quasi-floating gate transistors. This filter is suitable for channel filtering of highly integrated, ultra low power wireless receivers e.g. for Bluetooth and Zigbee. Measurement results for a test chip prototype in a low-cost 0.5µm standard CMOS process are presented

Using Digital Signal Processors on Small Satellites

Digital Signal Processing integrated circuits (DSPs) have improved terrestrial communications systems by allowing the implementation of greatly improved transmitters and receivers. In applications from dial-up modems, to echo-free conference phones, to customer-specific hearing aids, DSPs have allowed the implementation of functions that would be impractical without them. However, DSPs have had limited use in small satellites due to lower available data rates and relatively high power consumption. Also, most of the existing DSPs have not been space qualified. Improvements in semiconductor processes are allowing the construction of integrated circuits (ICs) with much smaller features. In fact, 0.6 micron processes are becoming generally available. Newer DSP ICs based on these processes have greater speeds and greatly reduced power consumption compared to their predecessors. This paper covers the general use of DSP ICs in small satellites, where the power consumption of on-board circuitry must be minimized. It then discusses DSP power consumption, the achievable DSP data rates, general radiation hardness for the existing DSPs, and the advantages and disadvantages of using DSP- based communication 1 systems in small satellites. The paper shows that the power consumption of presently available DSPs is now sufficiently low, and their processor speeds are now sufficiently high for application to some small satellite systems

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Low Power Implementation of Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

The DRM standard for digital radio broadcast in the AM band requires integrated devices for radio receivers at very low power. A System on Chip (SoC) call DiMITRI was developed based on a dual ARM9 RISC core architecture. Analyses showed that most computation power is used in the Coded Orthogonal Frequency Division Multiplexing (COFDM) demodulation to compute Fast Fourier Transforms (FFT) and inverse transforms (IFFT) on complex samples. These FFTs have to be computed on non power-of-two numbers of samples, which is very uncommon in the signal processing world. The results obtained with this chip, lead to the objective to decrease the power dissipated by the COFDM demodulation part using a coarse-grain reconfigurable structure as a coprocessor. This paper introduces two different coarse-grain architectures: PACT XPP technology and the Montium, developed by the University of Twente, and presents the implementation of a\ud Fast Fourier Transform on 1920 complex samples. The implementation result on the Montium shows a saving of a factor 35 in terms of processing time, and 14 in terms of power consumption compared to the RISC implementation, and a\ud smaller area. Then, as a conclusion, the paper presents the next steps of the development and some development issues

Highly Integrated THz Receiver Systems for Small Satellite Remote Sensing Applications

We are developing miniaturized, highly integrated Schottky receiver systems suitable for use in CubeSats or other small spacecraft platforms, where state-of-the-art performance and ultra-low mass, power, and volume are required. Current traditional Schottky receivers are too large to employ on a CubeSat. We will develop highly integrated receivers operating from 520-600 GHz and 1040-1200 GHz that are based on state-of-the-art receivers already developed at Jet Propulsion Laboratory (JPL) by using novel 3D multi layer packaging. This process will reduce both mass and volume by more than an order of magnitude, while preserving state-of-the-art noise performance. The resulting receiver systems will have a volume of approximately 25 x 25 x 40 millimeters (mm), a mass of 250 grams (g), and power consumption on the order of of 7 watts (W). Using these techniques, we will also integrate both receivers into a single frame, further reducing mass and volume for applications where dual band operation is advantageous. Additionally, as Schottky receivers offer significant gains in noise performance when cooled to 100 K, we will investigate the improvement gained by passively cooling these receivers. Work by Sierra Lobo Inc., with their Cryo Cube technology development program, offers the possibility of passive cooling to 100 K on CubeSat platforms for 1-unit (1U) sized instruments

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW

Wireless Information and Power Transfer: Architecture Design and Rate-Energy Tradeoff

Simultaneous information and power transfer over the wireless channels potentially offers great convenience to mobile users. Yet practical receiver designs impose technical constraints on its hardware realization, as practical circuits for harvesting energy from radio signals are not yet able to decode the carried information directly. To make theoretical progress, we propose a general receiver operation, namely, dynamic power splitting (DPS), which splits the received signal with adjustable power ratio for energy harvesting and information decoding, separately. Three special cases of DPS, namely, time switching (TS), static power splitting (SPS) and on-off power splitting (OPS) are investigated. The TS and SPS schemes can be treated as special cases of OPS. Moreover, we propose two types of practical receiver architectures, namely, separated versus integrated information and energy receivers. The integrated receiver integrates the front-end components of the separated receiver, thus achieving a smaller form factor. The rate-energy tradeoff for the two architectures are characterized by a so-called rate-energy (R-E) region. The optimal transmission strategy is derived to achieve different rate-energy tradeoffs. With receiver circuit power consumption taken into account, it is shown that the OPS scheme is optimal for both receivers. For the ideal case when the receiver circuit does not consume power, the SPS scheme is optimal for both receivers. In addition, we study the performance for the two types of receivers under a realistic system setup that employs practical modulation. Our results provide useful insights to the optimal practical receiver design for simultaneous wireless information and power transfer (SWIPT).Comment: to appear in IEEE Transactions on Communication

Energy-Detecting Receivers for Wake-Up Radio Applications

In the energy-limited wireless sensor node applications, wake-up radios are required to reduce the average power consumption of the node. Energy-detecting receivers are the best fit for such low power operations. This thesis presents the energy-detecting receiver design; challenges; techniques to enhance sensitivity, selectivity; and multi-access operation. Self-mixers instead of the conventional envelope detectors are proposed and proved to be optimal for signal detection. A fully integrated wake-up receiver uses the self-mixer and time-encoded baseband signal processing to provide a sensitivity of -79.1dBm at 434MHz with 420pW of power, providing an 8dB better sensitivity at 10dB lower power consumption compared to the SoA. A novel approach using narrowband interferers as local oscillators will be presented to further enhance sensitivity and selectivity, effectively operating the energy-detector receiver as a direct down-conversion receiver. Additionally, a clockless continuous-time analog correlator will be introduced to enhance the selectivity to wide-band AM interferers. The architecture uses pulse-position-encoded analog signal processing with VCOs as integrators and pulse-controlled relaxation delays; it operates as a code-domain matched filter to de-spread asynchronous wake-up codes. This code-domain matched filtering also provides code-division multiple access (CDMA) for simultaneous wakeups. Additional enhancement in the link can be achieved using directional antennas, providing spatial gain and selectivity. Certain applications can leverage a nearby reflector similar to a Yagi antenna to enhance the directivity. A low power directional backscatter tag is proposed, it uses multiple antennas acting as a reflectarray by configuring constant phase gradients depending on the direction of arrival (DoA) of the signal. Thus, instead of harvesting energy, the same energy and the surrounding environment can be leveraged to enhance functionality (e.g. interferer as LO, using a backscatter tag on a wall) for low power operation. Innovations spanning both system and circuit architectures that leverage the ambient energy and environment to enable power-efficient solutions for next-generation wake-up radios are presented in this work