3,122 research outputs found
Pavlov's dog associative learning demonstrated on synaptic-like organic transistors
In this letter, we present an original demonstration of an associative
learning neural network inspired by the famous Pavlov's dogs experiment. A
single nanoparticle organic memory field effect transistor (NOMFET) is used to
implement each synapse. We show how the physical properties of this dynamic
memristive device can be used to perform low power write operations for the
learning and implement short-term association using temporal coding and spike
timing dependent plasticity based learning. An electronic circuit was built to
validate the proposed learning scheme with packaged devices, with good
reproducibility despite the complex synaptic-like dynamic of the NOMFET in
pulse regime
Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing
How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one
A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC
The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at
the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a
radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is
presented. The design consists of two pipeline A/D channels each with four
Multiplying Digital-to-Analog Converters followed by 8-bit
Successive-Approximation-Register analog-to-digital converters. The custom
design, fabricated in a commercial 130 nm CMOS process, shows a performance of
67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5
ns (to first bit read out), while its total power consumption is 50 mW/channel.
The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to
single event effects during irradiation is measured and determined to meet the
system requirements
Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip
The ATLAS Collaboration will upgrade its semiconductor pixel tracking
detector with a new Insertable B-layer (IBL) between the existing pixel
detector and the vacuum pipe of the Large Hadron Collider. The extreme
operating conditions at this location have necessitated the development of new
radiation hard pixel sensor technologies and a new front-end readout chip,
called the FE-I4. Planar pixel sensors and 3D pixel sensors have been
investigated to equip this new pixel layer, and prototype modules using the
FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN
SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test
results are presented, including charge collection efficiency, tracking
efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS
Conception et mise au point de l'électronique frontale du détecteur de pied de gerbe (Preshower) de l'expérience CMS
Modern particle physics collider experiments consist of a number of macroscopic modules each consisting of large number of sensors measuring charge deposition from traversing particles. The CMS Preshower detector is designed as a sampling calorimeter producing electromagnetic showers for incident electrons and photons resulting from LHC p-p interactions. The ultimate aim is to provide neutral pion / gamma separation reducing the background to the most promising Higgs channel, SM Higgs to 2 photons. The detector has 4300 silicon sensors each subdivided into 32 channels with a total sensitive area of 16.4 m2. Front-end microelectronics ASICs must measure the charge of each channel accurately with low noise and over a wide dynamic range (4 fC to 1600 fC) at the rate of 40 MHz within a harsh radiation environment. This thesis presents the design and development of the Preshower front-end electronics ASIC development, PACE. The first chapter introduces the Preshower experiment and defines the specification for PACE as derived from the physics. The second chapter examines the radiation environment, its effect on electronic devices, and design techniques / technologies that can resist to LHC radiation levels. Chapters 3 to 5 present the design and results of two PACE developments examining analog memories based on current and voltage sampling techniques. Experimental results from a Preshower electro-mechanical prototype tested in a particle beam are also given
Low Power Memory/Memristor Devices and Systems
This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within
Confession Session: Learning from Others Mistakes
Accepted versio
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