9,412 research outputs found
Techniques for Improving Security and Trustworthiness of Integrated Circuits
The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuitโs gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects
๋ก์ง ๋ฐ ํผ์ง์ปฌ ํฉ์ฑ์์์ ํ์ด๋ฐ ๋ถ์๊ณผ ์ต์ ํ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2020. 8. ๊นํํ.Timing analysis is one of the necessary steps in the development of a semiconductor circuit. In addition, it is increasingly important in the advanced process technologies due to various factors, including the increase of processโvoltageโtemperature variation. This dissertation addresses three problems related to timing analysis and optimization in logic and physical synthesis. Firstly, most static timing analysis today are based on conventional fixed flip-flop timing models, in which every flip-flop is assumed to have a fixed clock-to-Q delay. However, setup and hold skews affect the clock-to-Q delay in reality. In this dissertation, I propose a mathematical formulation to solve the problem and apply it to the clock skew scheduling problems as well as to the analysis of a given circuit, with a scalable speedup technique. Secondly, near-threshold computing is one of the promising concepts for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, I propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime and advanced process technology. Lastly, an asynchronous circuit is one of the alternatives to the conventional synchronous style, and asynchronous pipeline circuit especially attractive because of its small design effort. This dissertation addresses the synthesis problem of lightening two-phase bundled-data asynchronous pipeline controllers, in which delay buffers are essential for guaranteeing the correct handshaking operation but incurs considerable area increase.ํ์ด๋ฐ ๋ถ์์ ๋ฐ๋์ฒด ํ๋ก ๊ฐ๋ฐ ํ์ ๊ณผ์ ์ค ํ๋๋ก, ์ต์ ๊ณต์ ์ผ์๋ก ๊ณต์ -์ ์-์จ๋ ๋ณ์ด ์ฆ๊ฐ๋ฅผ ํฌํจํ ๋ค์ํ ์์ธ์ผ๋ก ํ์ฌ๊ธ ๊ทธ ์ค์์ฑ์ด ์ปค์ง๊ณ ์๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ ๋ก์ง ๋ฐ ํผ์ง์ปฌ ํฉ์ฑ๊ณผ ๊ด๋ จํ์ฌ ์ธ ๊ฐ์ง ํ์ด๋ฐ ๋ถ์ ๋ฐ ์ต์ ํ ๋ฌธ์ ์ ๋ํด ๋ค๋ฃฌ๋ค. ์ฒซ์งธ๋ก, ์ค๋๋ ๋๋ถ๋ถ์ ์ ์ ํ์ด๋ฐ ๋ถ์์ ๋ชจ๋ ํ๋ฆฝ-ํ๋กญ์ ํด๋ญ-์ถ๋ ฅ ๋๋ ์ด๊ฐ ๊ณ ์ ๋ ๊ฐ์ด๋ผ๋ ๊ฐ์ ์ ๋ฐํ์ผ๋ก ์ด๋ฃจ์ด์ก๋ค. ํ์ง๋ง ์ค์ ํด๋ญ-์ถ๋ ฅ ๋๋ ์ด๋ ํด๋น ํ๋ฆฝ-ํ๋กญ์ ์
์
๋ฐ ํ๋ ์คํ์ ์ํฅ์ ๋ฐ๋๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ ์ด๋ฌํ ํน์ฑ์ ์ํ์ ์ผ๋ก ์ ๋ฆฌํ์์ผ๋ฉฐ, ์ด๋ฅผ ํ์ฅ ๊ฐ๋ฅํ ์๋ ํฅ์ ๊ธฐ๋ฒ๊ณผ ๋๋ถ์ด ์ฃผ์ด์ง ํ๋ก์ ํ์ด๋ฐ ๋ถ์ ๋ฐ ํด๋ญ ์คํ ์ค์ผ์ฅด๋ง ๋ฌธ์ ์ ์ ์ฉํ์๋ค. ๋์งธ๋ก, ์ ์ฌ ๋ฌธํฑ ์ฐ์ฐ์ ์ด๊ณ ์ง์ ํ๋ก ๋์์ ์๋์ง ํจ์จ์ ๋์ด ์ฌ๋ฆด ์ ์๋ค๋ ์ ์์ ๊ฐ๊ด๋ฐ์ง๋ง, ํฐ ํญ์ ์ฑ๋ฅ ๋ณ์ด ๋ฐ ๋น์ ํ์ฑ ๋๋ฌธ์ ๋๋ฆฌ ํ์ฉ๋๊ณ ์์ง ์๋ค. ์ด๋ฅผ ํด๊ฒฐํ๊ธฐ ์ํด ์ ์ฌ ๋ฌธํฑ ์ ์ ์์ญ ๋ฐ ์ต์ ๊ณต์ ๋
ธ๋์์ ๋ณด๋ค ์ ํํ ํ์ด๋ฐ ์์ธก์ ์ํ ํ๋์จ์ด ์ฑ๋ฅ ๋ชจ๋ํฐ๋ง ๋ฐฉ๋ฒ๋ก ์ ๋ฐ์ ์ ์ํ์๋ค. ๋ง์ง๋ง์ผ๋ก, ๋น๋๊ธฐ ํ๋ก๋ ๊ธฐ์กด ๋๊ธฐ ํ๋ก์ ๋์ ์ค ํ๋๋ก, ๊ทธ ์ค์์๋ ๋น๋๊ธฐ ํ์ดํ๋ผ์ธ ํ๋ก๋ ๋น๊ต์ ์ ์ ์ค๊ณ ๋
ธ๋ ฅ๋ง์ผ๋ก๋ ๊ตฌํ ๊ฐ๋ฅํ๋ค๋ ์ฅ์ ์ด ์๋ค. ๋ณธ ๋
ผ๋ฌธ์์๋ 2์์ ๋ฌถ์ ๋ฐ์ดํฐ ํ๋กํ ์ฝ ๊ธฐ๋ฐ ๋น๋๊ธฐ ํ์ดํ๋ผ์ธ ์ปจํธ๋กค๋ฌ ์์์, ์ ํํ ํธ๋์
ฐ์ดํน ํต์ ์ ์ํด ์ฝ์
๋ ๋๋ ์ด ๋ฒํผ์ ์ํ ๋ฉด์ ์ฆ๊ฐ๋ฅผ ์ํํ ์ ์๋ ํฉ์ฑ ๊ธฐ๋ฒ์ ์ ์ํ์๋ค.1 INTRODUCTION 1
1.1 Flexible Flip-Flop Timing Model 1
1.2 Hardware Performance Monitoring Methodology 4
1.3 Asynchronous Pipeline Controller 10
1.4 Contributions of this Dissertation 15
2 ANALYSIS AND OPTIMIZATION CONSIDERING FLEXIBLE FLIP-FLOP TIMING MODEL 17
2.1 Preliminaries 17
2.1.1 Terminologies 17
2.1.2 Timing Analysis 20
2.1.3 Clock-to-Q Delay Surface Modeling 21
2.2 Clock-to-Q Delay Interval Analysis 22
2.2.1 Derivation 23
2.2.2 Additional Constraints 26
2.2.3 Analysis: Finding Minimum Clock Period 28
2.2.4 Optimization: Clock Skew Scheduling 30
2.2.5 Scalable Speedup Technique 33
2.3 Experimental Results 37
2.3.1 Application to Minimum Clock Period Finding 37
2.3.2 Application to Clock Skew Scheduling 39
2.3.3 Efficacy of Scalable Speedup Technique 43
2.4 Summary 44
3 HARDWARE PERFORMANCE MONITORING METHODOLOGY AT NTC AND ADVANCED TECHNOLOGY NODE 45
3.1 Overall Flow of Proposed HPM Methodology 45
3.2 Prerequisites to HPM Methodology 47
3.2.1 BEOL Process Variation Modeling 47
3.2.2 Surrogate Model Preparation 49
3.3 HPM Methodology: Design Phase 52
3.3.1 HPM2PV Model Construction 52
3.3.2 Optimization of Monitoring Circuits Configuration 54
3.3.3 PV2CPT Model Construction 58
3.4 HPM Methodology: Post-Silicon Phase 60
3.4.1 Transfer Learning in Silicon Characterization Step 60
3.4.2 Procedures in Volume Production Phase 61
3.5 Experimental Results 62
3.5.1 Experimental Setup 62
3.5.2 Exploration of Monitoring Circuits Configuration 64
3.5.3 Effectiveness of Monitoring Circuits Optimization 66
3.5.4 Considering BEOL PVs and Uncertainty Learning 68
3.5.5 Comparison among Different Prediction Flows 69
3.5.6 Effectiveness of Prediction Model Calibration 71
3.6 Summary 73
4 LIGHTENING ASYNCHRONOUS PIPELINE CONTROLLER 75
4.1 Preliminaries and State-of-the-Art Work 75
4.1.1 Bundled-data vs. Dual-rail Asynchronous Circuits 75
4.1.2 Two-phase vs. Four-phase Bundled-data Protocol 76
4.1.3 Conventional State-of-the-Art Pipeline Controller Template 77
4.2 Delay Path Sharing for Lightening Pipeline Controller Template 78
4.2.1 Synthesizing Sharable Delay Paths 78
4.2.2 Validating Logical Correctness for Sharable Delay Paths 80
4.2.3 Reformulating Timing Constraints of Controller Template 81
4.2.4 Minimally Allocating Delay Buffers 87
4.3 In-depth Pipeline Controller Template Synthesis with Delay Path Reusing 88
4.3.1 Synthesizing Delay Path Units 88
4.3.2 Validating Logical Correctness of Delay Path Units 89
4.3.3 Updating Timing Constraints for Delay Path Units 91
4.3.4 In-depth Synthesis Flow Utilizing Delay Path Units 95
4.4 Experimental Results 99
4.4.1 Environment Setup 99
4.4.2 Piecewise Linear Modeling of Delay Path Unit Area 99
4.4.3 Comparison of Power, Performance, and Area 102
4.5 Summary 107
5 CONCLUSION 109
5.1 Chapter 2 109
5.2 Chapter 3 110
5.3 Chapter 4 110
Abstract (In Korean) 127Docto
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Improving timing verification and delay testing methodologies for IC designs
textThe task of ensuring the correct temporal behavior of IC designs,
both before and after fabrication, is extremely important. It is becoming
even more imperative as the demand for performance increases and process
technology advances into the deep sub-micron region.
This dissertation tackles the key issues in the timing verification
and delay testing methodologies. An efficient methodology is presented to
identify false timing paths in the timing verification methodology which utilizes
ATPG technique and timing information from an ordered list of timing
paths according to the delay information. This dissertation also presents a
speed binning methodology which utilizes structural delay tests successfully
instead of functional tests. In addition, it establishes a methodology which
quantifies the correlation between the timing verification prediction and
actual silicon measurement of timing paths. This quantification methodology
lays the foundation for further research to study the impact of deep
submicron effects on design performanceElectrical and Computer Engineerin
6T-SRAM 1Mb Design with Test Structures and Post Silicon Validation
abstract: Static random-access memories (SRAM) are integral part of design systems as caches and data memories that and occupy one-third of design space. The work presents an embedded low power SRAM on a triple well process that allows body-biasing control. In addition to the normal mode operation, the design is embedded with Physical Unclonable Function (PUF) [Suh07] and Sense Amplifier Test (SA Test) mode. With PUF mode structures, the fabrication and environmental mismatches in bit cells are used to generate unique identification bits. These bits are fixed and known as preferred state of an SRAM bit cell. The direct access test structure is a measurement unit for offset voltage analysis of sense amplifiers. These designs are manufactured using a foundry bulk CMOS 55 nm low-power (LP) process. The details about SRAM bit-cell and peripheral circuit design is discussed in detail, for certain cases the circuit simulation analysis is performed with random variations embedded in SPICE models. Further, post-silicon testing results are discussed for normal operation of SRAMs and the special test modes. The silicon and circuit simulation results for various tests are presented.Dissertation/ThesisMasters Thesis Electrical Engineering 201
Hardware Trojan Detection Using Controlled Circuit Aging
This paper reports a novel approach that uses transistor aging in an
integrated circuit (IC) to detect hardware Trojans. When a transistor is aged,
it results in delays along several paths of the IC. This increase in delay
results in timing violations that reveal as timing errors at the output of the
IC during its operation. We present experiments using aging-aware standard cell
libraries to illustrate the usefulness of the technique in detecting hardware
Trojans. Combining IC aging with over-clocking produces a pattern of bit errors
at the IC output by the induced timing violations. We use machine learning to
learn the bit error distribution at the output of a clean IC. We differentiate
the divergence in the pattern of bit errors because of a Trojan in the IC from
this baseline distribution. We simulate the golden IC and show robustness to
IC-to-IC manufacturing variations. The approach is effective and can detect a
Trojan even if we place it far off the critical paths. Results on benchmarks
from the Trust-hub show a detection accuracy of 99%.Comment: 21 pages, 34 figure
4-Dimensional Tracking with Ultra-Fast Silicon Detectors
The evolution of particle detectors has always pushed the technological limit
in order to provide enabling technologies to researchers in all fields of
science. One archetypal example is the evolution of silicon detectors, from a
system with a few channels 30 years ago, to the tens of millions of independent
pixels currently used to track charged particles in all major particle physics
experiments. Nowadays, silicon detectors are ubiquitous not only in research
laboratories but in almost every high-tech apparatus, from portable phones to
hospitals. In this contribution, we present a new direction in the evolution of
silicon detectors for charge particle tracking, namely the inclusion of very
accurate timing information. This enhancement of the present silicon detector
paradigm is enabled by the inclusion of controlled low gain in the detector
response, therefore increasing the detector output signal sufficiently to make
timing measurement possible. After providing a short overview of the advantage
of this new technology, we present the necessary conditions that need to be met
for both sensor and readout electronics in order to achieve 4-dimensional
tracking. In the last section we present the experimental results,
demonstrating the validity of our research path.Comment: 72 pages, 3 tables, 55 figure
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Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security.
In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented
Radiation Hardened by Design Methodologies for Soft-Error Mitigated Digital Architectures
abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies.
Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques.
A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
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