Cycle time optimization by timing driven placement with simultaneous netlist transformations

We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed

Discursive design thinking: the role of explicit knowledge in creative architectural design reasoning

The main hypothesis investigated in this paper is based upon the suggestion that the discursive reasoning in architecture supported by an explicit knowledge of spatial configurations can enhance both design productivity and the intelligibility of design solutions. The study consists of an examination of an architect’s performance while solving intuitively a well-defined problem followed by an analysis of the spatial structure of their design solutions. One group of architects will attempt to solve the design problem logically, rationalizing their design decisions by implementing their explicit knowledge of spatial configurations. The other group will use an implicit form of such knowledge arising from their architectural education to reason about their design acts. An integrated model of protocol analysis combining linkography and macroscopic coding is used to analyze the design processes. The resulting design outcomes will be evaluated quantitatively in terms of their spatial configurations. The analysis appears to show that an explicit knowledge of the rules of spatial configurations, as possessed by the first group of architects can partially enhance their function-driven judgment producing permeable and well-structured spaces. These findings are particularly significant as they imply that an explicit rather than an implicit knowledge of the fundamental rules that make a layout possible can lead to a considerable improvement in both the design process and product. This suggests that by externalizing th

Incremental placement for layout driven optimizations on FPGAs

This paper presents an algorithm to update the placement of logic elements when given an incremental netlist change. Specifically, these algorithms are targeted to incrementally place logic elements created by layout-driven circuit restruc-turing techniques. The incremental placement engine as-sumes that the restructuring algorithms provide a list of new logic elements along with preferred locations for each of these new elements. It then tries to shift non-critical logic elements in the original placement out of the way to satisfy the preferred location requests. Our algorithm considers modern FPGA architectures with clustered logic blocks that have numerous architectural constraints. Experiments indi-cate that our technique produces results of extremely high quality. 1

Fast Post-placement Rewiring Using Easily Detectable Functional Symmetries

Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear time algorithm is proposed to detect functional symmetries in the Boolean network and is used as the basis for rewiring. Integration with an existing gate sizing algorithm further proves the effectiveness of our technique. Experimental results are very promising

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Design methodology and productivity improvement in high speed VLSI circuits

2017 Spring.Includes bibliographical references.To view the abstract, please see the full text of the document