High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Resonant body transistors in standard CMOS technology

This work presents Si-based electromechanical resonators fabricated at the transistor level of a standard SOI CMOS technology and realized without the need for any postprocessing or packaging. These so-called Resonant Body Transistors (RBTs) are driven capacitively and sensed by piezoresistively modulating the drain current of a Field Effect Transistor (FET). First generation devices operating at 11.1-11.5 GHz with footprints of 3μm×5μm are demonstrated. These unreleased bulk acoustic resonators are completely buried within the CMOS stack and acoustic energy at resonance is confined using Acoustic Bragg Reflectors (ABRs). The complimentary TCE of Si/SiO[subscript 2] in the resonator and the surrounding ABRs results in a temperature stability TCF of <;3 ppm/K. Comparative behavior of devices is also discussed to analyze the effect of fabrication variations and active sensing.United States. National Security Agency. Trusted Access Program OfficeUnited States. Defense Advanced Research Projects Agency. Leading Edge Access ProgramIBM Researc

SI-based unreleased hybrid MEMS-CMOS resonators in 32nm technology

This work presents the first unreleased Silicon resonators fabricated at the transistor level of a standard CMOS process, and realized without any release steps or packaging. These unreleased bulk acoustic resonators are driven capacitively using the thin gate dielectric of the CMOS process, and actively sensed with a Field Effect Transistor (FET) incorporated into the resonant body. FET sensing using the high f[subscript T], high performance transistors in CMOS amplifies the mechanical signal before the presence of parasitics. This enables RF-MEMS resonators at orders of magnitude higher frequencies than possible with passive devices. First generation CMOS-MEMS Si resonators with Acoustic Bragg Reflectors are demonstrated at 11.1 GHz with Q~17 and a total footprint of 5μm × 3μm using IBM's 32nm SOI technology.United States. Defense Advanced Research Projects Agency. Leading Edge Access ProgramUnited States. National Security Agency. Trusted Access Program OfficeInternational Business Machines Corporatio

Towards Single-Chip Nano-Systems

Important scientific discoveries are being propelled by the advent of nano-scale sensors that capture weak signals from their environment and pass them to complex instrumentation interface circuits for signal detection and processing. The highlight of this research is to investigate fabrication technologies to integrate such precision equipment with nano-sensors on a single complementary metal oxide semiconductor (CMOS) chip. In this context, several demonstration vehicles are proposed. First, an integration technology suitable for a fully integrated flexible microelectrode array has been proposed. A microelectrode array containing a single temperature sensor has been characterized and the versatility under dry/wet, and relaxed/strained conditions has been verified. On-chip instrumentation amplifier has been utilized to improve the temperature sensitivity of the device. While the flexibility of the array has been confirmed by laminating it on a fixed single cell, future experiments are necessary to confirm application of this device for live cell and tissue measurements. The proposed array can potentially attach itself to the pulsating surface of a single living cell or a network of cells to detect their vital signs

Silicon on Nothing Mems Electromechanical Resonator

The very significant growth of the wireless communication industry has spawned tremendous interest in the development of high performances radio frequencies (RF) components. Micro Electro Mechanical Systems (MEMS) are good candidates to allow reconfigurable RF functions such as filters, oscillators or antennas. This paper will focus on the MEMS electromechanical resonators which show interesting performances to replace SAW filters or quartz reference oscillators, allowing smaller integrated functions with lower power consumption. The resonant frequency depends on the material properties, such as Young's modulus and density, and on the movable mechanical structure dimensions (beam length defined by photolithography). Thus, it is possible to obtain multi frequencies resonators on a wafer. The resonator performance (frequency, quality factor) strongly depends on the environment, like moisture or pressure, which imply the need for a vacuum package. This paper will present first resonator mechanisms and mechanical behaviors followed by state of the art descriptions with applications and specifications overview. Then MEMS resonator developments at STMicroelectronics including FEM analysis, technological developments and characterization are detailed.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Fabrication of SOI micromechanical devices

This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single crystal silicon micromechanical devices and basis for monolithic integration of sensors and integrated circuits. The buried oxide layer of an SOI wafer offers an excellent etch stop layer for silicon etching and sacrificial layer for fabrication of capacitive sensors. Deep silicon etching is studied and the aspect ratio dependency of the etch rate and loading effects are described and modeled. The etch rate of the deep silicon etching process is modeled with a simple flow conductance model, which takes into account only the initial etch rate and reaction probability and flow resistance of the etched feature. The used model predicts qualitatively the aspect-ratio-dependent etch rate for varying trench widths and rectangular shapes. The design related loading can be modeled and the effects of the loading can be minimized with proper etch mask design. The basic SOI micromechanics process is described and the drawbacks and limitations of the process are discussed. Improvements to the process are introduced as well as IR microscopy as a new method to inspect the sacrificial etch length of the SOI structure. A new fabrication process for SOI micromechanics has been developed that alleviates metallization problems during the wet etching of the sacrificial layer. The process is based on forming closed cavities under the structure layer of SOI with the help of a semi-permeable polysilicon film. Prototype SOI device fabrication results are presented. High Q single crystal silicon micro resonators have potential for replacing bulky quartz resonators in clock circuits. Monolithic integration of micromechanical devices and an integrated circuit has been demonstrated with the developed process using the embedded vacuum cavities.reviewe

CMOS systems and circuits for sub-degree per hour MEMS gyroscopes

The objective of our research is to develop system architectures and CMOS circuits that interface with high-Q silicon microgyroscopes to implement navigation-grade angular rate sensors. The MEMS sensor used in this work is an in-plane bulk-micromachined mode-matched tuning fork gyroscope (M² – TFG ), fabricated on silicon-on-insulator substrate. The use of CMOS transimpedance amplifiers (TIA) as front-ends in high-Q MEMS resonant sensors is explored. A T-network TIA is proposed as the front-end for resonant capacitive detection. The T-TIA provides on-chip transimpedance gains of 25MΩ, has a measured capacitive resolution of 0.02aF /√Hz at 15kHz, a dynamic range of 104dB in a bandwidth of 10Hz and consumes 400μW of power. A second contribution is the development of an automated scheme to adaptively bias the mechanical structure, such that the sensor is operated in the mode-matched condition. Mode-matching leverages the inherently high quality factors of the microgyroscope, resulting in significant improvement in the Brownian noise floor, electronic noise, sensitivity and bias drift of the microsensor. We developed a novel architecture that utilizes the often ignored residual quadrature error in a gyroscope to achieve and maintain perfect mode-matching (i.e.0Hz split between the drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS implementation is developed that allows mode-matching of the drive and sense frequencies of a gyroscope at a fraction of the time taken by current state of-the-art techniques. Further, this mode-matching technique allows for maintaining a controlled separation between the drive and sense resonant frequencies, providing a means of increasing sensor bandwidth and dynamic range. The mode-matching CMOS IC, implemented in a 0.5μm 2P3M process, and control algorithm have been interfaced with a 60μm thick M2−TFG to implement an angular rate sensor with bias drift as low as 0.1°/hr ℃ the lowest recorded to date for a silicon MEMS gyro.Ph.D.Committee Chair: Farrokh Ayazi; Committee Member: Jennifer Michaels; Committee Member: Levent Degertekin; Committee Member: Paul Hasler; Committee Member: W. Marshall Leac